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[PATCH v8 01/12] target/riscv: Fix PMU CSR predicate function
From: |
Atish Patra |
Subject: |
[PATCH v8 01/12] target/riscv: Fix PMU CSR predicate function |
Date: |
Wed, 11 May 2022 14:59:45 -0700 |
From: Atish Patra <atish.patra@wdc.com>
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/csr.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3500e07f92e1..ee3a35afa256 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -72,6 +72,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
+ int ctr_index;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
@@ -99,8 +100,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
@@ -126,8 +128,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
- if (!get_field(env->hcounteren, 1 << (csrno -
CSR_HPMCOUNTER3H)) &&
- get_field(env->mcounteren, 1 << (csrno -
CSR_HPMCOUNTER3H))) {
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
--
2.25.1
- [PATCH v8 00/12] Improve PMU support, Atish Patra, 2022/05/11
- [PATCH v8 01/12] target/riscv: Fix PMU CSR predicate function,
Atish Patra <=
- [PATCH v8 02/12] target/riscv: Implement PMU CSR predicate function for S-mode, Atish Patra, 2022/05/11
- [PATCH v8 03/12] target/riscv: pmu: Rename the counters extension to pmu, Atish Patra, 2022/05/11
- [PATCH v8 04/12] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2022/05/11
- [PATCH v8 05/12] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2022/05/11
- [PATCH v8 06/12] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2022/05/11
- [PATCH v8 08/12] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/05/11
- [PATCH v8 12/12] target/riscv: Update the privilege field for sscofpmf CSRs, Atish Patra, 2022/05/11
- [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2022/05/11