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[PATCH v2 2/6] hw/intc/arm_gicv3: report correct PRIbits field in ICV_CT
From: |
Peter Maydell |
Subject: |
[PATCH v2 2/6] hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1 |
Date: |
Thu, 12 May 2022 16:14:53 +0100 |
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is
supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the
virtual priority bit setting, not the physical priority bit setting.
(For QEMU currently we always implement 8 bits of physical priority,
so the PRIbits field was previously 7, since it is defined to be
"priority bits - 1".)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506162129.2896966-2-peter.maydell@linaro.org
---
hw/intc/arm_gicv3_cpuif.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index df2f8583564..ebf269b73a4 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -657,7 +657,7 @@ static uint64_t icv_ctlr_read(CPUARMState *env, const
ARMCPRegInfo *ri)
* should match the ones reported in ich_vtr_read().
*/
value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
- (7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
+ ((cs->vpribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT);
if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) {
value |= ICC_CTLR_EL1_EOIMODE;
--
2.25.1
- [PATCH v2 0/6] gicv3: Use right number of prio bits for the CPU, Peter Maydell, 2022/05/12
- [PATCH v2 3/6] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant, Peter Maydell, 2022/05/12
- [PATCH v2 1/6] hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters, Peter Maydell, 2022/05/12
- [PATCH v2 6/6] hw/intc/arm_gicv3: Provide ich_num_aprs(), Peter Maydell, 2022/05/12
- [PATCH v2 2/6] hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1,
Peter Maydell <=
- [PATCH v2 4/6] hw/intc/arm_gicv3: Support configurable number of physical priority bits, Peter Maydell, 2022/05/12
- [PATCH v2 5/6] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU, Peter Maydell, 2022/05/12