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[PATCH 2/5] target/riscv: Disable "G" by default
From: |
Tsukasa OI |
Subject: |
[PATCH 2/5] target/riscv: Disable "G" by default |
Date: |
Fri, 13 May 2022 18:45:47 +0900 |
Because "G" virtual extension expands to "IMAFD", we cannot separately
disable extensions like "F" or "D" without disabling "G". Because all
"IMAFD" are enabled by default, it's harmless to disable "G" by default.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 00bf26ec8b..3ea68d5cd7 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -812,7 +812,7 @@ static Property riscv_cpu_properties[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
- DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
+ DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
--
2.34.1
- [PATCH 0/5] target/riscv: Enhanced ISA extension checks, Tsukasa OI, 2022/05/13
- [PATCH 1/5] target/riscv: Fix "G" extension expansion typing, Tsukasa OI, 2022/05/13
- [PATCH 2/5] target/riscv: Disable "G" by default,
Tsukasa OI <=
- [PATCH 3/5] target/riscv: Change "G" expansion, Tsukasa OI, 2022/05/13
- [PATCH 4/5] target/riscv: FP extension requirements, Tsukasa OI, 2022/05/13
- [PATCH 5/5] target/riscv: Move/refactor ISA extension checks, Tsukasa OI, 2022/05/13
- [PATCH v2 0/5] target/riscv: Enhanced ISA extension checks, Tsukasa OI, 2022/05/14