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[PULL 35/91] cxl/cxl-host: Add memops for CFMWS region.
From: |
Michael S. Tsirkin |
Subject: |
[PULL 35/91] cxl/cxl-host: Add memops for CFMWS region. |
Date: |
Mon, 16 May 2022 06:37:39 -0400 |
From: Jonathan Cameron <jonathan.cameron@huawei.com>
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the current implementation does
not support:
* switches
* multiple HDM decoders at a given level.
* unaligned accesses across the interleave boundaries
Signed-off-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-Id: <20220429144110.25167-34-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/cxl/cxl.h | 2 +
hw/cxl/cxl-host-stubs.c | 2 +
hw/cxl/cxl-host.c | 128 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 132 insertions(+)
diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h
index dce38124db..21d28ca110 100644
--- a/include/hw/cxl/cxl.h
+++ b/include/hw/cxl/cxl.h
@@ -56,4 +56,6 @@ void cxl_fixed_memory_window_config(MachineState *ms,
Error **errp);
void cxl_fixed_memory_window_link_targets(Error **errp);
+extern const MemoryRegionOps cfmws_ops;
+
#endif
diff --git a/hw/cxl/cxl-host-stubs.c b/hw/cxl/cxl-host-stubs.c
index f8fd278d5d..24465a52ab 100644
--- a/hw/cxl/cxl-host-stubs.c
+++ b/hw/cxl/cxl-host-stubs.c
@@ -12,3 +12,5 @@ void cxl_fixed_memory_window_config(MachineState *ms,
Error **errp) {};
void cxl_fixed_memory_window_link_targets(Error **errp) {};
+
+const MemoryRegionOps cfmws_ops;
diff --git a/hw/cxl/cxl-host.c b/hw/cxl/cxl-host.c
index ec5a75cbf5..469b3c4ced 100644
--- a/hw/cxl/cxl-host.c
+++ b/hw/cxl/cxl-host.c
@@ -15,6 +15,10 @@
#include "qapi/qapi-visit-machine.h"
#include "hw/cxl/cxl.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci/pci_bridge.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci/pcie_port.h"
void cxl_fixed_memory_window_config(MachineState *ms,
CXLFixedMemoryWindowOptions *object,
@@ -92,3 +96,127 @@ void cxl_fixed_memory_window_link_targets(Error **errp)
}
}
}
+
+/* TODO: support, multiple hdm decoders */
+static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
+ uint8_t *target)
+{
+ uint32_t ctrl;
+ uint32_t ig_enc;
+ uint32_t iw_enc;
+ uint32_t target_reg;
+ uint32_t target_idx;
+
+ ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
+ if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) {
+ return false;
+ }
+
+ ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);
+ iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
+ target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
+
+ if (target_idx > 4) {
+ target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
+ target_reg >>= target_idx * 8;
+ } else {
+ target_reg = cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO];
+ target_reg >>= (target_idx - 4) * 8;
+ }
+ *target = target_reg & 0xff;
+
+ return true;
+}
+
+static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr)
+{
+ CXLComponentState *hb_cstate;
+ PCIHostState *hb;
+ int rb_index;
+ uint32_t *cache_mem;
+ uint8_t target;
+ bool target_found;
+ PCIDevice *rp, *d;
+
+ /* Address is relative to memory region. Convert to HPA */
+ addr += fw->base;
+
+ rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;
+ hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl.cxl_host_bridge);
+ if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) {
+ return NULL;
+ }
+
+ hb_cstate = cxl_get_hb_cstate(hb);
+ if (!hb_cstate) {
+ return NULL;
+ }
+
+ cache_mem = hb_cstate->crb.cache_mem_registers;
+
+ target_found = cxl_hdm_find_target(cache_mem, addr, &target);
+ if (!target_found) {
+ return NULL;
+ }
+
+ rp = pcie_find_port_by_pn(hb->bus, target);
+ if (!rp) {
+ return NULL;
+ }
+
+ d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0];
+
+ if (!d || !object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
+ return NULL;
+ }
+
+ return d;
+}
+
+static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ CXLFixedWindow *fw = opaque;
+ PCIDevice *d;
+
+ d = cxl_cfmws_find_device(fw, addr);
+ if (d == NULL) {
+ *data = 0;
+ /* Reads to invalid address return poison */
+ return MEMTX_ERROR;
+ }
+
+ return cxl_type3_read(d, addr + fw->base, data, size, attrs);
+}
+
+static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr,
+ uint64_t data, unsigned size,
+ MemTxAttrs attrs)
+{
+ CXLFixedWindow *fw = opaque;
+ PCIDevice *d;
+
+ d = cxl_cfmws_find_device(fw, addr);
+ if (d == NULL) {
+ /* Writes to invalid address are silent */
+ return MEMTX_OK;
+ }
+
+ return cxl_type3_write(d, addr + fw->base, data, size, attrs);
+}
+
+const MemoryRegionOps cfmws_ops = {
+ .read_with_attrs = cxl_read_cfmws,
+ .write_with_attrs = cxl_write_cfmws,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ .unaligned = true,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ .unaligned = true,
+ },
+};
--
MST
- [PULL 24/91] qtests/cxl: Add initial root port and CXL type3 tests, (continued)
- [PULL 24/91] qtests/cxl: Add initial root port and CXL type3 tests, Michael S. Tsirkin, 2022/05/16
- [PULL 25/91] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Michael S. Tsirkin, 2022/05/16
- [PULL 26/91] acpi/cxl: Add _OSC implementation (9.14.2), Michael S. Tsirkin, 2022/05/16
- [PULL 27/91] acpi/cxl: Create the CEDT (9.14.1), Michael S. Tsirkin, 2022/05/16
- [PULL 28/91] hw/cxl/component: Add utils for interleave parameter encoding/decoding, Michael S. Tsirkin, 2022/05/16
- [PULL 29/91] hw/cxl/host: Add support for CXL Fixed Memory Windows., Michael S. Tsirkin, 2022/05/16
- [PULL 30/91] acpi/cxl: Introduce CFMWS structures in CEDT, Michael S. Tsirkin, 2022/05/16
- [PULL 31/91] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Michael S. Tsirkin, 2022/05/16
- [PULL 32/91] pci/pcie_port: Add pci_find_port_by_pn(), Michael S. Tsirkin, 2022/05/16
- [PULL 33/91] CXL/cxl_component: Add cxl_get_hb_cstate(), Michael S. Tsirkin, 2022/05/16
- [PULL 35/91] cxl/cxl-host: Add memops for CFMWS region.,
Michael S. Tsirkin <=
- [PULL 34/91] mem/cxl_type3: Add read and write functions for associated hostmem., Michael S. Tsirkin, 2022/05/16
- [PULL 36/91] hw/cxl/component Add a dumb HDM decoder handler, Michael S. Tsirkin, 2022/05/16
- [PULL 37/91] i386/pc: Enable CXL fixed memory windows, Michael S. Tsirkin, 2022/05/16
- [PULL 39/91] qtests/bios-tables-test: Add a test for CXL emulation., Michael S. Tsirkin, 2022/05/16
- [PULL 38/91] tests/acpi: q35: Allow addition of a CXL test., Michael S. Tsirkin, 2022/05/16
- [PULL 40/91] tests/acpi: Add tables for CXL emulation., Michael S. Tsirkin, 2022/05/16
- [PULL 41/91] qtest/cxl: Add more complex test cases with CFMWs, Michael S. Tsirkin, 2022/05/16
- [PULL 42/91] docs/cxl: Add initial Compute eXpress Link (CXL) documentation., Michael S. Tsirkin, 2022/05/16
- [PULL 43/91] vhost: Track descriptor chain in private at SVQ, Michael S. Tsirkin, 2022/05/16
- [PULL 44/91] vhost: Fix device's used descriptor dequeue, Michael S. Tsirkin, 2022/05/16