[PULL v2 39/86] qtests/bios-tables-test: Add a test for CXL emulation.

[Michael S. Tsirkin]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

The DSDT includes several CXL specific elements and the CEDT
table is only present if we enable CXL.

The test exercises all current functionality with several
CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC
entries in DSDT.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20220429144110.25167-38-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 tests/qtest/bios-tables-test.c | 44 ++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 5dddedabcd..a4a46e97f0 100644
--- a/tests/qtest/bios-tables-test.c
+++ b/tests/qtest/bios-tables-test.c
@@ -1536,6 +1536,49 @@ static void test_acpi_q35_viot(void)
     free_test_data(&data);
 }
 
+static void test_acpi_q35_cxl(void)
+{
+    gchar *tmp_path = g_dir_make_tmp("qemu-test-cxl.XXXXXX", NULL);
+    gchar *params;
+
+    test_data data = {
+        .machine = MACHINE_Q35,
+        .variant = ".cxl",
+    };
+    /*
+     * A complex CXL setup.
+     */
+    params = g_strdup_printf(" -machine cxl=on"
+                             " -object 
memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M"
+                             " -object 
memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M"
+                             " -object 
memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M"
+                             " -object 
memory-backend-file,id=cxl-mem4,mem-path=%s,size=256M"
+                             " -object 
memory-backend-file,id=lsa1,mem-path=%s,size=256M"
+                             " -object 
memory-backend-file,id=lsa2,mem-path=%s,size=256M"
+                             " -object 
memory-backend-file,id=lsa3,mem-path=%s,size=256M"
+                             " -object 
memory-backend-file,id=lsa4,mem-path=%s,size=256M"
+                             " -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1"
+                             " -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2"
+                             " -device 
cxl-rp,port=0,bus=cxl.1,id=rp1,chassis=0,slot=2"
+                             " -device 
cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1"
+                             " -device 
cxl-rp,port=1,bus=cxl.1,id=rp2,chassis=0,slot=3"
+                             " -device 
cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2"
+                             " -device 
cxl-rp,port=0,bus=cxl.2,id=rp3,chassis=0,slot=5"
+                             " -device 
cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3"
+                             " -device 
cxl-rp,port=1,bus=cxl.2,id=rp4,chassis=0,slot=6"
+                             " -device 
cxl-type3,bus=rp4,memdev=cxl-mem4,lsa=lsa4"
+                             " -cxl-fixed-memory-window 
targets.0=cxl.1,size=4G,interleave-granularity=8k"
+                             " -cxl-fixed-memory-window 
targets.0=cxl.1,targets.1=cxl.2,size=4G,interleave-granularity=8k",
+                             tmp_path, tmp_path, tmp_path, tmp_path,
+                             tmp_path, tmp_path, tmp_path, tmp_path);
+    test_acpi_one(params, &data);
+
+    g_free(params);
+    g_assert(g_rmdir(tmp_path) == 0);
+    g_free(tmp_path);
+    free_test_data(&data);
+}
+
 static void test_acpi_virt_viot(void)
 {
     test_data data = {
@@ -1741,6 +1784,7 @@ int main(int argc, char *argv[])
             qtest_add_func("acpi/q35/kvm/dmar", test_acpi_q35_kvm_dmar);
         }
         qtest_add_func("acpi/q35/viot", test_acpi_q35_viot);
+        qtest_add_func("acpi/q35/cxl", test_acpi_q35_cxl);
         qtest_add_func("acpi/q35/slic", test_acpi_q35_slic);
     } else if (strcmp(arch, "aarch64") == 0) {
         if (has_tcg) {
-- 
MST