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Re: [PULL 00/22] target-arm queue
From: |
Richard Henderson |
Subject: |
Re: [PULL 00/22] target-arm queue |
Date: |
Thu, 19 May 2022 13:29:03 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 |
On 5/19/22 10:36, Peter Maydell wrote:
target-arm queue: mostly patches from me this time round.
Nothing too exciting.
-- PMM
The following changes since commit 78ac2eebbab9150edf5d0d00e3648f5ebb599001:
Merge tag 'artist-cursor-fix-final-pull-request' of
https://github.com/hdeller/qemu-hppa into staging (2022-05-18 09:32:15 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220519
for you to fetch changes up to fab8ad39fb75a0d9f097db67b2a334444754e88e:
target/arm: Use FIELD definitions for CPACR, CPTR_ELx (2022-05-19 18:34:10
+0100)
----------------------------------------------------------------
target-arm queue:
* Implement FEAT_S2FWB
* Implement FEAT_IDST
* Drop unsupported_encoding() macro
* hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
* Fix aarch64 debug register names
* hw/adc/zynq-xadc: Use qemu_irq typedef
* target/arm/helper.c: Delete stray obsolete comment
* Make number of counters in PMCR follow the CPU
* hw/arm/virt: Fix dtb nits
* ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
* target/arm: Fix PAuth keys access checks for disabled SEL2
* Enable FEAT_HCX for -cpu max
* Use FIELD definitions for CPACR, CPTR_ELx
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as
appropriate.
r~
----------------------------------------------------------------
Chris Howard (1):
Fix aarch64 debug register names.
Florian Lugou (1):
target/arm: Fix PAuth keys access checks for disabled SEL2
Peter Maydell (17):
target/arm: Postpone interpretation of stage 2 descriptor attribute bits
target/arm: Factor out FWB=0 specific part of combine_cacheattrs()
target/arm: Implement FEAT_S2FWB
target/arm: Enable FEAT_S2FWB for -cpu max
target/arm: Implement FEAT_IDST
target/arm: Drop unsupported_encoding() macro
hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters
hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1
hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant
hw/intc/arm_gicv3: Support configurable number of physical priority bits
hw/intc/arm_gicv3: Use correct number of priority bits for the CPU
hw/intc/arm_gicv3: Provide ich_num_aprs()
target/arm/helper.c: Delete stray obsolete comment
target/arm: Make number of counters in PMCR follow the CPU
hw/arm/virt: Fix incorrect non-secure flash dtb node name
hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node
ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY
Philippe Mathieu-Daudé (1):
hw/adc/zynq-xadc: Use qemu_irq typedef
Richard Henderson (2):
target/arm: Enable FEAT_HCX for -cpu max
target/arm: Use FIELD definitions for CPACR, CPTR_ELx
docs/system/arm/emulation.rst | 2 +
include/hw/adc/zynq-xadc.h | 3 +-
include/hw/intc/arm_gicv3_common.h | 8 +-
include/hw/ptimer.h | 16 +-
target/arm/cpregs.h | 24 +++
target/arm/cpu.h | 76 +++++++-
target/arm/internals.h | 11 +-
target/arm/translate-a64.h | 9 -
hw/adc/zynq-xadc.c | 4 +-
hw/arm/boot.c | 2 +-
hw/arm/musicpal.c | 2 +-
hw/arm/virt.c | 4 +-
hw/core/machine.c | 4 +-
hw/dma/xilinx_axidma.c | 2 +-
hw/dma/xlnx_csu_dma.c | 2 +-
hw/intc/arm_gicv3_common.c | 5 +
hw/intc/arm_gicv3_cpuif.c | 225 +++++++++++++++++-------
hw/intc/arm_gicv3_kvm.c | 16 +-
hw/m68k/mcf5206.c | 2 +-
hw/m68k/mcf5208.c | 2 +-
hw/net/can/xlnx-zynqmp-can.c | 2 +-
hw/net/fsl_etsec/etsec.c | 2 +-
hw/net/lan9118.c | 2 +-
hw/rtc/exynos4210_rtc.c | 4 +-
hw/timer/allwinner-a10-pit.c | 2 +-
hw/timer/altera_timer.c | 2 +-
hw/timer/arm_timer.c | 2 +-
hw/timer/digic-timer.c | 2 +-
hw/timer/etraxfs_timer.c | 6 +-
hw/timer/exynos4210_mct.c | 6 +-
hw/timer/exynos4210_pwm.c | 2 +-
hw/timer/grlib_gptimer.c | 2 +-
hw/timer/imx_epit.c | 4 +-
hw/timer/imx_gpt.c | 2 +-
hw/timer/mss-timer.c | 2 +-
hw/timer/sh_timer.c | 2 +-
hw/timer/slavio_timer.c | 2 +-
hw/timer/xilinx_timer.c | 2 +-
target/arm/cpu.c | 11 +-
target/arm/cpu64.c | 30 ++++
target/arm/cpu_tcg.c | 6 +
target/arm/helper.c | 348 ++++++++++++++++++++++++++++---------
target/arm/kvm64.c | 12 ++
target/arm/op_helper.c | 9 +
target/arm/translate-a64.c | 36 +++-
tests/unit/ptimer-test.c | 6 +-
46 files changed, 697 insertions(+), 228 deletions(-)
- [PULL 15/22] target/arm/helper.c: Delete stray obsolete comment, (continued)
- [PULL 15/22] target/arm/helper.c: Delete stray obsolete comment, Peter Maydell, 2022/05/19
- [PULL 13/22] Fix aarch64 debug register names., Peter Maydell, 2022/05/19
- [PULL 18/22] hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node, Peter Maydell, 2022/05/19
- [PULL 19/22] ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY, Peter Maydell, 2022/05/19
- [PULL 20/22] target/arm: Fix PAuth keys access checks for disabled SEL2, Peter Maydell, 2022/05/19
- [PULL 17/22] hw/arm/virt: Fix incorrect non-secure flash dtb node name, Peter Maydell, 2022/05/19
- [PULL 21/22] target/arm: Enable FEAT_HCX for -cpu max, Peter Maydell, 2022/05/19
- [PULL 16/22] target/arm: Make number of counters in PMCR follow the CPU, Peter Maydell, 2022/05/19
- [PULL 22/22] target/arm: Use FIELD definitions for CPACR, CPTR_ELx, Peter Maydell, 2022/05/19
- [PULL 08/22] hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1, Peter Maydell, 2022/05/19
- Re: [PULL 00/22] target-arm queue,
Richard Henderson <=