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[PATCH v5 15/43] target/loongarch: Add branch instruction translation
From: |
Xiaojuan Yang |
Subject: |
[PATCH v5 15/43] target/loongarch: Add branch instruction translation |
Date: |
Tue, 24 May 2022 16:17:36 +0800 |
From: Song Gao <gaosong@loongson.cn>
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
.../loongarch/insn_trans/trans_branch.c.inc | 83 +++++++++++++++++++
target/loongarch/insns.decode | 28 +++++++
target/loongarch/translate.c | 1 +
3 files changed, 112 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_branch.c.inc
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc
b/target/loongarch/insn_trans/trans_branch.c.inc
new file mode 100644
index 0000000000..65dbdff41e
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+static bool trans_b(DisasContext *ctx, arg_b *a)
+{
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_bl(DisasContext *ctx, arg_bl *a)
+{
+ tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ tcg_gen_addi_tl(cpu_pc, src1, a->offs);
+ tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+ tcg_gen_lookup_and_goto_ptr();
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static void gen_bc(DisasContext *ctx, TCGv src1, TCGv src2,
+ target_long offs, TCGCond cond)
+{
+ TCGLabel *l = gen_new_label();
+ tcg_gen_brcond_tl(cond, src1, src2, l);
+ gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
+ gen_set_label(l);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + offs);
+ ctx->base.is_jmp = DISAS_NORETURN;
+}
+
+static bool gen_rr_bc(DisasContext *ctx, arg_rr_offs *a, TCGCond cond)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
+
+ gen_bc(ctx, src1, src2, a->offs, cond);
+ return true;
+}
+
+static bool gen_rz_bc(DisasContext *ctx, arg_r_offs *a, TCGCond cond)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = tcg_constant_tl(0);
+
+ gen_bc(ctx, src1, src2, a->offs, cond);
+ return true;
+}
+
+static bool gen_cz_bc(DisasContext *ctx, arg_c_offs *a, TCGCond cond)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_constant_tl(0);
+
+ tcg_gen_ld8u_tl(src1, cpu_env,
+ offsetof(CPULoongArchState, cf[a->cj]));
+ gen_bc(ctx, src1, src2, a->offs, cond);
+ return true;
+}
+
+TRANS(beq, gen_rr_bc, TCG_COND_EQ)
+TRANS(bne, gen_rr_bc, TCG_COND_NE)
+TRANS(blt, gen_rr_bc, TCG_COND_LT)
+TRANS(bge, gen_rr_bc, TCG_COND_GE)
+TRANS(bltu, gen_rr_bc, TCG_COND_LTU)
+TRANS(bgeu, gen_rr_bc, TCG_COND_GEU)
+TRANS(beqz, gen_rz_bc, TCG_COND_EQ)
+TRANS(bnez, gen_rz_bc, TCG_COND_NE)
+TRANS(bceqz, gen_cz_bc, TCG_COND_EQ)
+TRANS(bcnez, gen_cz_bc, TCG_COND_NE)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 8f286e7233..9b293dfdf9 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -10,6 +10,9 @@
#
%i14s2 10:s14 !function=shl_2
%sa2p1 15:2 !function=plus_1
+%offs21 0:s5 10:16 !function=shl_2
+%offs16 10:s16 !function=shl_2
+%offs26 0:s10 10:16 !function=shl_2
#
# Argument sets
@@ -38,6 +41,10 @@
&rc rd cj
&frr fd rj rk
&fr_i fd rj imm
+&r_offs rj offs
+&c_offs cj offs
+&offs offs
+&rr_offs rj rd offs
#
# Formats
@@ -74,6 +81,10 @@
@rc .... ........ ..... ..... .. cj:3 rd:5 &rc
@frr .... ........ ..... rk:5 rj:5 fd:5 &frr
@fr_i12 .... ...... imm:s12 rj:5 fd:5 &fr_i
+@r_offs21 .... .. ................ rj:5 ..... &r_offs
offs=%offs21
+@c_offs21 .... .. ................ .. cj:3 ..... &c_offs
offs=%offs21
+@offs26 .... .. .......................... &offs
offs=%offs26
+@rr_offs16 .... .. ................ rj:5 rd:5 &rr_offs
offs=%offs16
#
# Fixed point arithmetic operation instruction
@@ -409,3 +420,20 @@ fstgt_s 0011 10000111 01100 ..... ..... .....
@frr
fstgt_d 0011 10000111 01101 ..... ..... ..... @frr
fstle_s 0011 10000111 01110 ..... ..... ..... @frr
fstle_d 0011 10000111 01111 ..... ..... ..... @frr
+
+#
+# Branch instructions
+#
+beqz 0100 00 ................ ..... ..... @r_offs21
+bnez 0100 01 ................ ..... ..... @r_offs21
+bceqz 0100 10 ................ 00 ... ..... @c_offs21
+bcnez 0100 10 ................ 01 ... ..... @c_offs21
+jirl 0100 11 ................ ..... ..... @rr_offs16
+b 0101 00 .......................... @offs26
+bl 0101 01 .......................... @offs26
+beq 0101 10 ................ ..... ..... @rr_offs16
+bne 0101 11 ................ ..... ..... @rr_offs16
+blt 0110 00 ................ ..... ..... @rr_offs16
+bge 0110 01 ................ ..... ..... @rr_offs16
+bltu 0110 10 ................ ..... ..... @rr_offs16
+bgeu 0110 11 ................ ..... ..... @rr_offs16
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 6a3fffdbe0..e850c55b0c 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -171,6 +171,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend
dst_ext)
#include "insn_trans/trans_fcnv.c.inc"
#include "insn_trans/trans_fmov.c.inc"
#include "insn_trans/trans_fmemory.c.inc"
+#include "insn_trans/trans_branch.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
2.31.1
- [PATCH v5 07/43] target/loongarch: Add fixed point load/store instruction translation, (continued)
- [PATCH v5 07/43] target/loongarch: Add fixed point load/store instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 06/43] target/loongarch: Add fixed point bit instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 01/43] target/loongarch: Add README, Xiaojuan Yang, 2022/05/24
- [PATCH v5 10/43] target/loongarch: Add floating point arithmetic instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 08/43] target/loongarch: Add fixed point atomic instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 12/43] target/loongarch: Add floating point conversion instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 11/43] target/loongarch: Add floating point comparison instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 05/43] target/loongarch: Add fixed point shift instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 19/43] target/loongarch: Add CSRs definition, Xiaojuan Yang, 2022/05/24
- [PATCH v5 13/43] target/loongarch: Add floating point move instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 15/43] target/loongarch: Add branch instruction translation,
Xiaojuan Yang <=
- [PATCH v5 21/43] target/loongarch: Implement qmp_query_cpu_definitions(), Xiaojuan Yang, 2022/05/24
- [PATCH v5 24/43] target/loongarch: Add constant timer support, Xiaojuan Yang, 2022/05/24
- [PATCH v5 20/43] target/loongarch: Add basic vmstate description of CPU., Xiaojuan Yang, 2022/05/24
- [PATCH v5 14/43] target/loongarch: Add floating point load/store instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 02/43] target/loongarch: Add core definition, Xiaojuan Yang, 2022/05/24
- [PATCH v5 22/43] target/loongarch: Add MMU support for LoongArch CPU., Xiaojuan Yang, 2022/05/24
- [PATCH v5 37/43] hw/loongarch: Add some devices support for 3A5000., Xiaojuan Yang, 2022/05/24
- [PATCH v5 03/43] target/loongarch: Add main translation routines, Xiaojuan Yang, 2022/05/24
- [PATCH v5 27/43] target/loongarch: Add TLB instruction support, Xiaojuan Yang, 2022/05/24
- [PATCH v5 28/43] target/loongarch: Add other core instructions support, Xiaojuan Yang, 2022/05/24