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[PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage
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From: |
Alistair Francis |
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Subject: |
[PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage |
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Date: |
Wed, 25 May 2022 08:44:28 +1000 |
From: Bin Meng <bin.meng@windriver.com>
VxWorks 7 uses the same boot interface as the Linux kernel on Arm
(64-bit only), PowerPC and RISC-V architectures. Add logic to set
is_linux to true for VxWorks uImage for these architectures in
load_uboot_image().
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220324134812.541274-2-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/core/loader.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 8167301f04..edde657ac3 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -696,6 +696,21 @@ static int load_uboot_image(const char *filename, hwaddr
*ep, hwaddr *loadaddr,
if (is_linux) {
if (hdr->ih_os == IH_OS_LINUX) {
*is_linux = 1;
+ } else if (hdr->ih_os == IH_OS_VXWORKS) {
+ /*
+ * VxWorks 7 uses the same boot interface as the Linux kernel
+ * on Arm (64-bit only), PowerPC and RISC-V architectures.
+ */
+ switch (hdr->ih_arch) {
+ case IH_ARCH_ARM64:
+ case IH_ARCH_PPC:
+ case IH_ARCH_RISCV:
+ *is_linux = 1;
+ break;
+ default:
+ *is_linux = 0;
+ break;
+ }
} else {
*is_linux = 0;
}
--
2.35.3
- [PULL 12/23] target/riscv: Move/refactor ISA extension checks, (continued)
- [PULL 12/23] target/riscv: Move/refactor ISA extension checks, Alistair Francis, 2022/05/24
- [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors, Alistair Francis, 2022/05/24
- [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize, Alistair Francis, 2022/05/24
- [PULL 16/23] target/riscv: Fix typo of mimpid cpu option, Alistair Francis, 2022/05/24
- [PULL 17/23] target/riscv: Fix csr number based privilege checking, Alistair Francis, 2022/05/24
- [PULL 18/23] target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode, Alistair Francis, 2022/05/24
- [PULL 19/23] target/riscv: Set [m|s]tval for both illegal and virtual instruction traps, Alistair Francis, 2022/05/24
- [PULL 20/23] hw/riscv: virt: Fix interrupt parent for dynamic platform devices, Alistair Francis, 2022/05/24
- [PULL 21/23] target/riscv: add zicsr/zifencei to isa_string, Alistair Francis, 2022/05/24
- [PULL 22/23] hw/core: Sync uboot_image.h from U-Boot v2022.01, Alistair Francis, 2022/05/24
- [PULL 23/23] hw/core: loader: Set is_linux to true for VxWorks uImage,
Alistair Francis <=
- [PULL 11/23] target/riscv: FP extension requirements, Alistair Francis, 2022/05/24
- Re: [PULL 00/23] riscv-to-apply queue, Richard Henderson, 2022/05/24