Re: [PATCH 5/8] pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.

[Paolo Bonzini]

On 5/30/22 15:45, Jonathan Cameron via wrote:
> +    /* Walk the pci busses looking for pxb busses to hook up */
> +    if (bus) {
> +        QLIST_FOREACH(bus, &bus->child, sibling) {
> +            if (!pci_bus_is_root(bus)) {
> +                continue;
> +            }
> +            if (pci_bus_is_cxl(bus)) {
> +                if (!ms->cxl_devices_state->is_enabled) {
> +                    error_report("CXL host bridges present, but cxl=off");
> +                    exit(EXIT_FAILURE);
> +                }
> +                pxb_cxl_hook_up_registers(ms->cxl_devices_state, bus, 
> &error_fatal);
> +            }
> +        }
> +    }

Perhaps this loop can be moved to a separate function in cxl_host.h?

Otherwise looks great, thank you very much for the quick reply!

Paolo

>       if (ms->cxl_devices_state) {
>           cxl_fmws_link_targets(ms->cxl_devices_state, &error_fatal);
>       }