Re: [PATCH v5 0/1] target/riscv: Add Zihintpause support

[Alistair Francis]

On Wed, Aug 3, 2022 at 9:42 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Sun, Jul 24, 2022 at 9:39 PM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Mon, Jul 25, 2022 at 1:48 PM Dao Lu <daolu@rivosinc.com> wrote:
> > >
> > > This patch adds RISC-V Zihintpause support. The extension is set to be 
> > > enabled
> > > by default and opcode has been added to insn32.decode.
> > >
> > > Added trans_pause to exit the TB and return to main loop.
> > >
> > > The change can also be found in:
> > > https://github.com/dlu42/qemu/tree/zihintpause_support_v1
> > >
> > > Tested along with pause support added to cpu_relax function for linux, the
> > > changes I made to linux to test can be found here:
> > > https://github.com/dlu42/linux/tree/pause_support_v1
> > >
> > > --------
> > > Changelog:
> > >
> > > v1 -> v2
> > > 1. Pause now also exit the TB and return to main loop
> > > 2. Move the REQUIRE_ZIHINTPAUSE macro inside the trans_pause function
> > >
> > > v2 -> v3
> > > No changes, v2 was lost from the list
> > >
> > > v3 -> v4
> > > No longer break the reservation in trans_pause
> > >
> > > v4 -> v5
> > > Rabase on top of 
> > > https://github.com/alistair23/qemu/tree/riscv-to-apply.next
> > >
> > > Dao Lu (1):
> > >   Add Zihintpause support
> >
> > Thanks!
> >
> > Applied to riscv-to-apply.next
> >
>
> Did you overwrite your tree by mistake ? I pulled riscv-to-apply.next
> a few days back where this patch along with Anup's priv version
> fixes are there. But I can't find it anymore. I am looking at this.

Hey Atish,

I created a last minute pull request to get some fixes into 7.1. When
I did that I overwrote the current riscv-to-apply.next with a version
that only has a few bug fixes.

I have pushed the riscv-to-apply.next for 7.2 to my public repo again.

Alistair

>
> https://github.com/alistair23/qemu/commits/riscv-to-apply.next
>
> I wanted to rebase my sstc series on top of the riscv-to-apply.next.
> Let me know if I am missing something.
>
> > Alistair
> >
> > >
> > >  target/riscv/cpu.c                      |  2 ++
> > >  target/riscv/cpu.h                      |  1 +
> > >  target/riscv/insn32.decode              |  7 ++++++-
> > >  target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++++
> > >  4 files changed, 25 insertions(+), 1 deletion(-)
> > >
> > > --
> > > 2.25.1
> > >
> > >
> >
>
>
> --
> Regards,
> Atish