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[PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model
From: |
Cédric Le Goater |
Subject: |
[PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model |
Date: |
Tue, 9 Aug 2022 17:38:48 +0200 |
The Device Control Registers (DCR) of on-SoC devices are accessed by
software through the use of the mtdcr and mfdcr instructions. These
are converted in transactions on a side band bus, the DCR bus, which
connects the on-SoC devices to the CPU.
Ideally, we should model these accesses with a DCR namespace and DCR
memory regions but today the DCR handlers are installed in a DCR table
under the CPU. Instead introduce a little device model wrapper to hold
a CPU link and handle registration of DCR handlers.
The DCR device inherits from SysBus because most of these devices also
have MMIO regions and/or IRQs. Being a SysBusDevice makes things easier
to install the device model in the overall SoC.
The "cpu" link should be considered as modeling the piece of HW logic
connecting the device to the DCR bus.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/ppc4xx.h | 17 ++++++++++++++++
hw/ppc/ppc4xx_devs.c | 44 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
index 591e2421a343..82e60b0e0742 100644
--- a/include/hw/ppc/ppc4xx.h
+++ b/include/hw/ppc/ppc4xx.h
@@ -27,6 +27,7 @@
#include "hw/ppc/ppc.h"
#include "exec/memory.h"
+#include "hw/sysbus.h"
void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
MemoryRegion ram_memories[],
@@ -44,4 +45,20 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum,
uint8_t rxcnum,
#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
+/*
+ * Generic DCR device
+ */
+#define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
+struct Ppc4xxDcrDeviceState {
+ SysBusDevice parent_obj;
+
+ PowerPCCPU *cpu;
+};
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write);
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+ Error **errp);
+
#endif /* PPC4XX_H */
diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
index 069b51195160..bce7ef461346 100644
--- a/hw/ppc/ppc4xx_devs.c
+++ b/hw/ppc/ppc4xx_devs.c
@@ -664,3 +664,47 @@ void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum,
uint8_t rxcnum,
mal, &dcr_read_mal, &dcr_write_mal);
}
}
+
+void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn,
+ dcr_read_cb dcr_read, dcr_write_cb dcr_write)
+{
+ CPUPPCState *env;
+
+ assert(dev->cpu);
+
+ env = &dev->cpu->env;
+
+ ppc_dcr_register(env, dcrn, dev, dcr_read, dcr_write);
+}
+
+bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
+ Error **errp)
+{
+ object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
+ return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
+}
+
+static Property ppc4xx_dcr_properties[] = {
+ DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
+ PowerPCCPU *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ device_class_set_props(dc, ppc4xx_dcr_properties);
+}
+
+static const TypeInfo ppc4xx_types[] = {
+ {
+ .name = TYPE_PPC4xx_DCR_DEVICE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Ppc4xxDcrDeviceState),
+ .class_init = ppc4xx_dcr_class_init,
+ .abstract = true,
+ }
+};
+
+DEFINE_TYPES(ppc4xx_types)
--
2.37.1
- [PATCH v4 04/24] ppc/ppc405: Move SRAM under the ref405ep machine, (continued)
- [PATCH v4 04/24] ppc/ppc405: Move SRAM under the ref405ep machine, Cédric Le Goater, 2022/08/09
- [PATCH v4 03/24] ppc/ppc405: Move devices under the ref405ep machine, Cédric Le Goater, 2022/08/09
- [PATCH v4 02/24] ppc/ppc405: Introduce a PPC405 generic machine, Cédric Le Goater, 2022/08/09
- [PATCH v4 01/24] ppc/ppc405: Remove taihu machine, Cédric Le Goater, 2022/08/09
- [PATCH v4 05/24] ppc/ppc405: Introduce a PPC405 SoC, Cédric Le Goater, 2022/08/09
- [PATCH v4 06/24] ppc/ppc405: Start QOMification of the SoC, Cédric Le Goater, 2022/08/09
- [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model,
Cédric Le Goater <=
- Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model, BALATON Zoltan, 2022/08/09
- Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model, Cédric Le Goater, 2022/08/10
- Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model, BALATON Zoltan, 2022/08/10
- Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model, Cédric Le Goater, 2022/08/10
- Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model, BALATON Zoltan, 2022/08/10
- Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model, Cédric Le Goater, 2022/08/11
- Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model, BALATON Zoltan, 2022/08/11
- Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model, Cédric Le Goater, 2022/08/11
- Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model, BALATON Zoltan, 2022/08/11
[PATCH v4 07/24] ppc/ppc405: QOM'ify CPU, Cédric Le Goater, 2022/08/09