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Re: [PATCH 7/7] target/riscv: Honour -semihosting-config userspace=on an
From: |
Alistair Francis |
Subject: |
Re: [PATCH 7/7] target/riscv: Honour -semihosting-config userspace=on and enable=on |
Date: |
Thu, 18 Aug 2022 14:19:52 +1000 |
On Tue, Aug 16, 2022 at 5:11 AM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The riscv target incorrectly enabled semihosting always, whether the
> user asked for it or not. Call semihosting_enabled() passing the
> correct value to the is_userspace argument, which fixes this and also
> handles the userspace=on argument.
>
> Note that this is a behaviour change: we used to default to
> semihosting being enabled, and now the user must pass
> "-semihosting-config enable=on" if they want it.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
I agree with Richard that a check in translate would be better, but
this is also an improvement on the broken implementation we have now
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_helper.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 59b3680b1b2..49c4ea98ac9 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -24,6 +24,7 @@
> #include "exec/exec-all.h"
> #include "tcg/tcg-op.h"
> #include "trace.h"
> +#include "semihosting/semihost.h"
> #include "semihosting/common-semi.h"
>
> int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
> @@ -1342,7 +1343,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> target_ulong mtval2 = 0;
>
> if (cause == RISCV_EXCP_SEMIHOST) {
> - if (env->priv >= PRV_S) {
> + if (semihosting_enabled(env->priv < PRV_S)) {
> do_common_semihosting(cs);
> env->pc += 4;
> return;
> --
> 2.25.1
>
>
- Re: [PATCH 3/7] target/m68k: Honour -semihosting-config userspace=on, (continued)
[PATCH 2/7] target/arm: Honour -semihosting-config userspace=on, Peter Maydell, 2022/08/15
Re: [PATCH 0/7] Allow semihosting from user mode, Richard Henderson, 2022/08/15