Re: [PATCH for-7.1 3/4] target/loongarch: rename the TCG CPU "la464" to "qemu64-v1.00"

[Richard Henderson]

On 8/17/22 19:31, WANG Xuerui wrote:
> Hmm, I've looked up more context and it is indeed reasonable to generally name the QEMU 
> models after real existing models. But in this case we could face a problem with 
> Loongson's nomenclature: all of Loongson 3A5000, 3C5000 and 3C5000L are LA464, yet they 
> should be distinguishable software-side by checking the model name CSR. But with only one 
> CPU model that is LA464, currently this CSR is hard-coded to read "3A5000", and this can 
> hurt IMO. And when we finally add LA264 and LA364 they would be identical ISA-level-wise, 
> again the only differentiator is the model name CSR.

Indeed, I believe that I pointed this out during review, and asked for loongarch_qemu_read 
to be moved.  But apparently I missed it the next time around, and it snuck in.  There's 
nothing in that memory region that is related to the core.


> And by "not high-fidelity", I mean some of the features present on real HW might never get 
> implemented, or actually implementable, like the DVFS mechanism needed by cpufreq.

Certainly we can add stub versions of any such registers.  Such things are extremely 
common under target/arm/.

> Lastly, the "ISA level" I proposed is not arbitrarily made up; it's direct reference to 
> the ISA manual revision. Each time the ISA gets some addition/revision the ISA manual has 
> to be updated, and currently the manual's revision is the only reliable source of said 
> information. (Loongson has a history of naming cores badly, like with the MIPS 3B1500 and 
> 3A4000, both were "GS464V"; and 3A5000 was originally GS464V too, even though the insn 
> encodings and some semantics have been entirely different.)

That is a good argument for your isa level scheme, at least as aliases.


r~