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Re: [PATCH v2] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic


From: Peter Maydell
Subject: Re: [PATCH v2] hw/net/can: fix Xilinx ZynqMP CAN RX FIFO logic
Date: Wed, 24 Aug 2022 20:25:14 +0100

On Wed, 17 Aug 2022 at 15:33, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Wed, 17 Aug 2022 at 15:24, Anton Kochkov <anton.kochkov@proton.me> wrote:
> >
> > For consistency, function "update_rx_fifo()" should use
> > the RX FIFO register names, not the TX FIFO ones even if
>
> "register field names"
>
> > they refer to the same memory region.
>
> "same bit positions in the register".
>
> (No need to spin a v3 just for that; if there's no other
> issues with the patch I'll fix it up when I take it into
> target-arm.next.)

Richard, since you're accumulating target-arm patches currently,
could you pick this one up (with the commit message fixups), please?

thanks
-- PMM



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