[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH-for-8.0 7/7] hw/mips/malta: Use bootloader generator API for nano
|
From: |
Philippe Mathieu-Daudé |
|
Subject: |
[PATCH-for-8.0 7/7] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs |
|
Date: |
Sat, 10 Dec 2022 16:55:02 +0100 |
Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader
helper to set BAR registers") converted write_bootloader(), convert
the equivalent write_bootloader_nanomips(), allowing us to modify
the bootloader code more easily in the future.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/mips/malta.c | 148 ++++++++++++------------------------------------
1 file changed, 35 insertions(+), 113 deletions(-)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 944730af98..d0da0b71eb 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -614,6 +614,7 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
uint64_t kernel_entry)
{
uint16_t *p;
+ void *v;
/* Small bootloader */
p = (uint16_t *)base;
@@ -682,123 +683,44 @@ static void write_bootloader_nanomips(uint8_t *base,
uint64_t run_addr,
stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
/* ori a3,a3,%lo(loaderparams.ram_low_size) */
- /*
- * Load BAR registers as done by YAMON:
- *
- * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
- * - set up PCI0 MEM0 at 0x10000000, size 0x8000000
- * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
- *
- */
- stw_p(p++, 0xe040); stw_p(p++, 0x0681);
- /* lui t1, %hi(0xb4000000) */
-
#if TARGET_BIG_ENDIAN
-
- stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
- /* lui t0, %hi(0xdf000000) */
-
- /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */
- stw_p(p++, 0x8422); stw_p(p++, 0x9068);
- /* sw t0, 0x68(t1) */
-
- stw_p(p++, 0xe040); stw_p(p++, 0x077d);
- /* lui t1, %hi(0xbbe00000) */
-
- stw_p(p++, 0xe020); stw_p(p++, 0x0801);
- /* lui t0, %hi(0xc0000000) */
-
- /* 0x48 corresponds to GT_PCI0IOLD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9048);
- /* sw t0, 0x48(t1) */
-
- stw_p(p++, 0xe020); stw_p(p++, 0x0800);
- /* lui t0, %hi(0x40000000) */
-
- /* 0x50 corresponds to GT_PCI0IOHD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9050);
- /* sw t0, 0x50(t1) */
-
- stw_p(p++, 0xe020); stw_p(p++, 0x0001);
- /* lui t0, %hi(0x80000000) */
-
- /* 0x58 corresponds to GT_PCI0M0LD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9058);
- /* sw t0, 0x58(t1) */
-
- stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
- /* lui t0, %hi(0x3f000000) */
-
- /* 0x60 corresponds to GT_PCI0M0HD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9060);
- /* sw t0, 0x60(t1) */
-
- stw_p(p++, 0xe020); stw_p(p++, 0x0821);
- /* lui t0, %hi(0xc1000000) */
-
- /* 0x80 corresponds to GT_PCI0M1LD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9080);
- /* sw t0, 0x80(t1) */
-
- stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
- /* lui t0, %hi(0x5e000000) */
-
+#define cpu_to_gt32 cpu_to_le32
#else
-
- stw_p(p++, 0x0020); stw_p(p++, 0x00df);
- /* addiu[32] t0, $0, 0xdf */
-
- /* 0x68 corresponds to GT_ISD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9068);
- /* sw t0, 0x68(t1) */
-
- /* Use kseg2 remapped address 0x1be00000 */
- stw_p(p++, 0xe040); stw_p(p++, 0x077d);
- /* lui t1, %hi(0xbbe00000) */
-
- stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
- /* addiu[32] t0, $0, 0xc0 */
-
- /* 0x48 corresponds to GT_PCI0IOLD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9048);
- /* sw t0, 0x48(t1) */
-
- stw_p(p++, 0x0020); stw_p(p++, 0x0040);
- /* addiu[32] t0, $0, 0x40 */
-
- /* 0x50 corresponds to GT_PCI0IOHD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9050);
- /* sw t0, 0x50(t1) */
-
- stw_p(p++, 0x0020); stw_p(p++, 0x0080);
- /* addiu[32] t0, $0, 0x80 */
-
- /* 0x58 corresponds to GT_PCI0M0LD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9058);
- /* sw t0, 0x58(t1) */
-
- stw_p(p++, 0x0020); stw_p(p++, 0x003f);
- /* addiu[32] t0, $0, 0x3f */
-
- /* 0x60 corresponds to GT_PCI0M0HD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9060);
- /* sw t0, 0x60(t1) */
-
- stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
- /* addiu[32] t0, $0, 0xc1 */
-
- /* 0x80 corresponds to GT_PCI0M1LD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9080);
- /* sw t0, 0x80(t1) */
-
- stw_p(p++, 0x0020); stw_p(p++, 0x005e);
- /* addiu[32] t0, $0, 0x5e */
-
+#define cpu_to_gt32 cpu_to_be32
#endif
+ v = p;
- /* 0x88 corresponds to GT_PCI0M1HD */
- stw_p(p++, 0x8422); stw_p(p++, 0x9088);
- /* sw t0, 0x88(t1) */
+ /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+ bl_gen_write_u32(&v, /* GT_ISD */
+ cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
+ cpu_to_gt32(0x1be00000 << 3));
+
+ /* setup MEM-to-PCI0 mapping */
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ bl_gen_write_u32(&v, /* GT_PCI0IOLD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
+ cpu_to_gt32(0x18000000 << 3));
+ bl_gen_write_u32(&v, /* GT_PCI0IOHD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
+ cpu_to_gt32(0x08000000 << 3));
+ /* setup PCI0 mem windows */
+ bl_gen_write_u32(&v, /* GT_PCI0M0LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
+ cpu_to_gt32(0x10000000 << 3));
+ bl_gen_write_u32(&v, /* GT_PCI0M0HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
+ cpu_to_gt32(0x07e00000 << 3));
+
+ bl_gen_write_u32(&v, /* GT_PCI0M1LD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
+ cpu_to_gt32(0x18200000 << 3));
+ bl_gen_write_u32(&v, /* GT_PCI0M1HD */
+ cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
+ cpu_to_gt32(0x0bc00000 << 3));
+
+ p = (uint16_t *)v;
+
+#undef cpu_to_gt32
stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
--
2.38.1