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Re: [PATCH v5 5/7] hw/isa/vt82c686: Work around missing level sensitive


From: Bernhard Beschow
Subject: Re: [PATCH v5 5/7] hw/isa/vt82c686: Work around missing level sensitive irq in i8259 model
Date: Wed, 01 Mar 2023 06:49:01 +0000


Am 1. März 2023 00:17:11 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>:
>MorphOS sets the ISA PIC to level sensitive mode but QEMU does not
>support that so this causes a freeze if multiple devices try to raise
>a shared interrupt. Work around it by lowering the interrupt before
>raising it again if it is already raised. This could be reverted when
>the i8259 model is fixed.
>
>Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>---
> hw/isa/vt82c686.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
>diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
>index 018a119964..3e44a51f92 100644
>--- a/hw/isa/vt82c686.c
>+++ b/hw/isa/vt82c686.c
>@@ -549,6 +549,7 @@ struct ViaISAState {
>     PCIDevice dev;
>     qemu_irq cpu_intr;
>     qemu_irq *isa_irqs_in;
>+    uint16_t isa_irqs_state;
>     ViaSuperIOState via_sio;
>     MC146818RtcState rtc;
>     PCIIDEState ide;
>@@ -636,6 +637,14 @@ static void via_isa_set_pci_irq(void *opaque, int 
>irq_num, int level)
>             pic_level |= pci_bus_get_irq_level(bus, i);
>         }
>     }
>+    /* FIXME: workaround for i8259: level sensitive irq not supported */
>+    if ((s->isa_irqs_state & BIT(pic_irq)) && pic_level) {
>+        qemu_irq_lower(s->isa_irqs_in[pic_irq]);
>+    } else if (pic_level) {
>+        s->isa_irqs_state |= BIT(pic_irq);
>+    } else {
>+        s->isa_irqs_state &= ~BIT(pic_irq);
>+    }

Let's not clutter the device model with workarounds which quickly snowball into 
unmaintainable code. Please fix the i8259 instead.

>     /* Now we change the pic irq level according to the via irq mappings. */
>     qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
> }



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