> object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004,
> &error_abort);
> object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
> @@ -191,6 +192,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error
> **errp)
> const MemMapEntry *memmap = sifive_e_memmap;
> SiFiveESoCState *s = RISCV_E_SOC(dev);
> MemoryRegion *sys_mem = get_system_memory();
> + unsigned int cpus = machine_topo_get_cpus(ms);
>
> object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
> &error_abort);
> @@ -204,7 +206,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error
> **errp)
>
> /* MMIO */
> s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
> - (char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0,
> + (char *)SIFIVE_E_PLIC_HART_CONFIG, cpus, 0,
> SIFIVE_E_PLIC_NUM_SOURCES,
> SIFIVE_E_PLIC_NUM_PRIORITIES,
> SIFIVE_E_PLIC_PRIORITY_BASE,
> @@ -215,10 +217,10 @@ static void sifive_e_soc_realize(DeviceState *dev,
> Error **errp)
> SIFIVE_E_PLIC_CONTEXT_STRIDE,
> memmap[SIFIVE_E_DEV_PLIC].size);
> riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
> - 0, ms->smp.cpus, false);
> + 0, cpus, false);
> riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
> RISCV_ACLINT_SWI_SIZE,
> - RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
> + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, cpus,
> RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
> RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, false);
> create_unimplemented_device("riscv.sifive.e.aon",
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index d3ab7a9cda5d..c7f969510209 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -99,7 +99,7 @@ static void create_fdt(SiFiveUState *s, const
> MemMapEntry *memmap,
> MachineState *ms = MACHINE(s);
> uint64_t mem_size = ms->ram_size;
> void *fdt;
> - int cpu, fdt_size;
> + int cpu, fdt_size, num_cpus = machine_topo_get_cpus(ms);
> uint32_t *cells;
> char *nodename;
> uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
> @@ -175,7 +175,7 @@ static void create_fdt(SiFiveUState *s, const
> MemMapEntry *memmap,
> qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
> qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
>
> - for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
> + for (cpu = num_cpus - 1; cpu >= 0; cpu--) {
> int cpu_phandle = phandle++;
> nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
> char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller",
cpu);
> @@ -207,8 +207,8 @@ static void create_fdt(SiFiveUState *s, const
> MemMapEntry *memmap,
> g_free(nodename);
> }
>
> - cells = g_new0(uint32_t, ms->smp.cpus * 4);
> - for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + cells = g_new0(uint32_t, num_cpus * 4);
> + for (cpu = 0; cpu < num_cpus; cpu++) {
> nodename =
> g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
> uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
> @@ -227,7 +227,7 @@ static void create_fdt(SiFiveUState *s, const
> MemMapEntry *memmap,
> 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
> 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
> qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
> - cells, ms->smp.cpus * sizeof(uint32_t) * 4);
> + cells, num_cpus * sizeof(uint32_t) * 4);
> g_free(cells);
> g_free(nodename);
>
> @@ -258,8 +258,8 @@ static void create_fdt(SiFiveUState *s, const
> MemMapEntry *memmap,
> g_free(nodename);
>
> plic_phandle = phandle++;
> - cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
> - for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + cells = g_new0(uint32_t, machine_topo_get_cpus(ms) * 4 - 2);
> + for (cpu = 0; cpu < machine_topo_get_cpus(ms); cpu++) {
> nodename =
> g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
> uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
> @@ -283,7 +283,7 @@ static void create_fdt(SiFiveUState *s, const
> MemMapEntry *memmap,
> (char **)&plic_compat, ARRAY_SIZE(plic_compat));
> qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
> qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
> - cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
> + cells, (machine_topo_get_cpus(ms) * 4 - 2) * sizeof(uint32_t));
> qemu_fdt_setprop_cells(fdt, nodename, "reg",
> 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
> 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
> @@ -797,10 +797,10 @@ static void sifive_u_soc_realize(DeviceState *dev,
> Error **errp)
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> char *plic_hart_config;
> - int i, j;
> + int i, j, cpus = machine_topo_get_cpus(ms);
> NICInfo *nd = &nd_table[0];
>
> - qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
> + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", cpus - 1);
> qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
> qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
> qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
> @@ -837,11 +837,11 @@ static void sifive_u_soc_realize(DeviceState *dev,
> Error **errp)
> l2lim_mem);
>
> /* create PLIC hart topology configuration string */
> - plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
> + plic_hart_config = riscv_plic_hart_config_string(cpus);
>
> /* MMIO */
> s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
> - plic_hart_config, ms->smp.cpus, 0,
> + plic_hart_config, cpus, 0,
> SIFIVE_U_PLIC_NUM_SOURCES,
> SIFIVE_U_PLIC_NUM_PRIORITIES,
> SIFIVE_U_PLIC_PRIORITY_BASE,
> @@ -857,10 +857,10 @@ static void sifive_u_soc_realize(DeviceState *dev,
> Error **errp)
> sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
> serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
> riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0,
> - ms->smp.cpus, false);
> + cpus, false);
> riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base +
> RISCV_ACLINT_SWI_SIZE,
> - RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
> + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, cpus,
> RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
> CLINT_TIMEBASE_FREQ, false);
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index b81081c70b1c..4b0a3dab5ec1 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -506,16 +506,17 @@ static void create_fdt_imsic(RISCVVirtState *s, const
> MemMapEntry *memmap,
> char *imsic_name;
> MachineState *ms = MACHINE(s);
> int socket_count = riscv_socket_count(ms);
> - uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
> + uint32_t imsic_max_hart_per_socket, imsic_guest_bits, cpus;
> uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
>
> + cpus = machine_topo_get_cpus(ms);
> *msi_m_phandle = (*phandle)++;
> *msi_s_phandle = (*phandle)++;
> - imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2);
> + imsic_cells = g_new0(uint32_t, cpus * 2);
> imsic_regs = g_new0(uint32_t, socket_count * 4);
>
> /* M-level IMSIC node */
> - for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + for (cpu = 0; cpu < cpus; cpu++) {
> imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
> imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
> }
> @@ -544,7 +545,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const
> MemMapEntry *memmap,
> qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
> NULL, 0);
> qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
> - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
> + imsic_cells, cpus * sizeof(uint32_t) * 2);
> qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
> socket_count * sizeof(uint32_t) * 4);
> qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
> @@ -562,7 +563,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const
> MemMapEntry *memmap,
> g_free(imsic_name);
>
> /* S-level IMSIC node */
> - for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
> + for (cpu = 0; cpu < cpus; cpu++) {
> imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
> imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
> }
> @@ -593,7 +594,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const
> MemMapEntry *memmap,
> qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller",
> NULL, 0);
> qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended",
> - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2);
> + imsic_cells, cpus * sizeof(uint32_t) * 2);
> qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs,
> socket_count * sizeof(uint32_t) * 4);
> qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids",
> @@ -732,7 +733,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const
> MemMapEntry *memmap,
> char *clust_name;
> int socket, phandle_pos;
> MachineState *ms = MACHINE(s);
> - uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
> + uint32_t msi_m_phandle = 0, msi_s_phandle = 0, cpus;
> uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
> int socket_count = riscv_socket_count(ms);
>
> @@ -743,9 +744,10 @@ static void create_fdt_sockets(RISCVVirtState *s, const
> MemMapEntry *memmap,
> qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
> qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
>
> - intc_phandles = g_new0(uint32_t, ms->smp.cpus);
> + cpus = machine_topo_get_cpus(ms);
> + intc_phandles = g_new0(uint32_t, cpus);
>
> - phandle_pos = ms->smp.cpus;
> + phandle_pos = cpus;
> for (socket = (socket_count - 1); socket >= 0; socket--) {
> phandle_pos -= s->soc[socket].num_harts;
>
> @@ -776,7 +778,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const
> MemMapEntry *memmap,
> *msi_pcie_phandle = msi_s_phandle;
> }
>
> - phandle_pos = ms->smp.cpus;
> + phandle_pos = cpus;
> for (socket = (socket_count - 1); socket >= 0; socket--) {
> phandle_pos -= s->soc[socket].num_harts;
>
> @@ -1113,7 +1115,7 @@ static FWCfgState *create_fw_cfg(const
> MachineState *ms)
>
> fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
> &address_space_memory);
> - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
> + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS,
> (uint16_t)machine_topo_get_cpus(ms));
>
> return fw_cfg;
> }
> --
> 2.34.1