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[PULL 4/5] target/loongarch: Implement Chip Configuraiton Version Regist
From: |
Song Gao |
Subject: |
[PULL 4/5] target/loongarch: Implement Chip Configuraiton Version Register(0x0000) |
Date: |
Fri, 3 Mar 2023 10:41:02 +0800 |
According to the 3A5000 manual 4.1 implement Chip Configuration
Version Register(0x0000).
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230227071046.1445572-1-gaosong@loongson.cn>
---
target/loongarch/cpu.c | 2 ++
target/loongarch/cpu.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index d6513f2d9d..97e6579f6a 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -546,6 +546,8 @@ static void loongarch_qemu_write(void *opaque, hwaddr addr,
static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
{
switch (addr) {
+ case VERSION_REG:
+ return 0x11ULL;
case FEATURE_REG:
return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
1ULL << IOCSRF_CSRIPI;
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index d60693fafe..e11c875188 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -28,6 +28,7 @@
#define IOCSRF_GMOD 9
#define IOCSRF_VM 11
+#define VERSION_REG 0x0
#define FEATURE_REG 0x8
#define VENDOR_REG 0x10
#define CPUNAME_REG 0x20
--
2.31.1
- [PULL 0/5] loongarch-to-apply queue, Song Gao, 2023/03/02
- [PULL 5/5] hw/loongarch/virt: add system_powerdown hmp command support, Song Gao, 2023/03/02
- [PULL 1/5] hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE, Song Gao, 2023/03/02
- [PULL 4/5] target/loongarch: Implement Chip Configuraiton Version Register(0x0000),
Song Gao <=
- [PULL 3/5] docs/system/loongarch: update loongson3.rst and rename it to virt.rst, Song Gao, 2023/03/02
- [PULL 2/5] loongarch: Add smbios command line option., Song Gao, 2023/03/02
- Re: [PULL 0/5] loongarch-to-apply queue, Peter Maydell, 2023/03/04