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[PULL 11/21] target/arm: Implement gdbstub pauth extension
From: |
Peter Maydell |
Subject: |
[PULL 11/21] target/arm: Implement gdbstub pauth extension |
Date: |
Mon, 6 Mar 2023 15:34:25 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
ptrace register set.
The original gdb feature consists of two masks, data and code, which are
used to mask out the authentication code within a pointer. Following
discussion with Luis Machado, add two more masks in order to support
pointers within the high half of the address space (i.e. TTBR1 vs TTBR0).
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230227213329.793795-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
configs/targets/aarch64-linux-user.mak | 2 +-
configs/targets/aarch64-softmmu.mak | 2 +-
configs/targets/aarch64_be-linux-user.mak | 2 +-
target/arm/internals.h | 2 ++
target/arm/gdbstub.c | 5 ++++
target/arm/gdbstub64.c | 34 +++++++++++++++++++++++
gdb-xml/aarch64-pauth.xml | 15 ++++++++++
7 files changed, 59 insertions(+), 3 deletions(-)
create mode 100644 gdb-xml/aarch64-pauth.xml
diff --git a/configs/targets/aarch64-linux-user.mak
b/configs/targets/aarch64-linux-user.mak
index db552f18390..ba8bc5fe3fd 100644
--- a/configs/targets/aarch64-linux-user.mak
+++ b/configs/targets/aarch64-linux-user.mak
@@ -1,6 +1,6 @@
TARGET_ARCH=aarch64
TARGET_BASE_ARCH=arm
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
gdb-xml/aarch64-pauth.xml
TARGET_HAS_BFLT=y
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/configs/targets/aarch64-softmmu.mak
b/configs/targets/aarch64-softmmu.mak
index d489e6da830..b4338e95680 100644
--- a/configs/targets/aarch64-softmmu.mak
+++ b/configs/targets/aarch64-softmmu.mak
@@ -1,5 +1,5 @@
TARGET_ARCH=aarch64
TARGET_BASE_ARCH=arm
TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml
gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
gdb-xml/arm-m-profile-mve.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml
gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml
gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml
TARGET_NEED_FDT=y
diff --git a/configs/targets/aarch64_be-linux-user.mak
b/configs/targets/aarch64_be-linux-user.mak
index dc78044fb15..acb5620cdbf 100644
--- a/configs/targets/aarch64_be-linux-user.mak
+++ b/configs/targets/aarch64_be-linux-user.mak
@@ -1,7 +1,7 @@
TARGET_ARCH=aarch64
TARGET_BASE_ARCH=arm
TARGET_BIG_ENDIAN=y
-TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml
gdb-xml/aarch64-pauth.xml
TARGET_HAS_BFLT=y
CONFIG_SEMIHOSTING=y
CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c891c7a3831..dda89aa5dff 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1349,6 +1349,8 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray
*buf, int reg);
int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);
int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);
int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index bf8aff78241..062c8d447a0 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -355,6 +355,11 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
aarch64_gdb_set_fpu_reg,
34, "aarch64-fpu.xml", 0);
}
+ if (isar_feature_aa64_pauth(&cpu->isar)) {
+ gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,
+ aarch64_gdb_set_pauth_reg,
+ 4, "aarch64-pauth.xml", 0);
+ }
#endif
} else {
if (arm_feature(env, ARM_FEATURE_NEON)) {
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 3d9e9e97c86..3bee892fb76 100644
--- a/target/arm/gdbstub64.c
+++ b/target/arm/gdbstub64.c
@@ -210,6 +210,40 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t
*buf, int reg)
return 0;
}
+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)
+{
+ switch (reg) {
+ case 0: /* pauth_dmask */
+ case 1: /* pauth_cmask */
+ case 2: /* pauth_dmask_high */
+ case 3: /* pauth_cmask_high */
+ /*
+ * Note that older versions of this feature only contained
+ * pauth_{d,c}mask, for use with Linux user processes, and
+ * thus exclusively in the low half of the address space.
+ *
+ * To support system mode, and to debug kernels, two new regs
+ * were added to cover the high half of the address space.
+ * For the purpose of pauth_ptr_mask, we can use any well-formed
+ * address within the address space half -- here, 0 and -1.
+ */
+ {
+ bool is_data = !(reg & 1);
+ bool is_high = reg & 2;
+ uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);
+ return gdb_get_reg64(buf, mask);
+ }
+ default:
+ return 0;
+ }
+}
+
+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)
+{
+ /* All pseudo registers are read-only. */
+ return 0;
+}
+
static void output_vector_union_type(GString *s, int reg_width,
const char *name)
{
diff --git a/gdb-xml/aarch64-pauth.xml b/gdb-xml/aarch64-pauth.xml
new file mode 100644
index 00000000000..24af5f903c1
--- /dev/null
+++ b/gdb-xml/aarch64-pauth.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.aarch64.pauth">
+ <reg name="pauth_dmask" bitsize="64"/>
+ <reg name="pauth_cmask" bitsize="64"/>
+ <reg name="pauth_dmask_high" bitsize="64"/>
+ <reg name="pauth_cmask_high" bitsize="64"/>
+</feature>
+
--
2.34.1
- [PULL 04/21] target/arm: Split out output_vector_union_type, (continued)
- [PULL 04/21] target/arm: Split out output_vector_union_type, Peter Maydell, 2023/03/06
- [PULL 03/21] target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.c, Peter Maydell, 2023/03/06
- [PULL 07/21] target/arm: Fix svep width in arm_gen_dynamic_svereg_xml, Peter Maydell, 2023/03/06
- [PULL 08/21] target/arm: Add name argument to output_vector_union_type, Peter Maydell, 2023/03/06
- [PULL 10/21] target/arm: Create pauth_ptr_mask, Peter Maydell, 2023/03/06
- [PULL 06/21] target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xml, Peter Maydell, 2023/03/06
- [PULL 12/21] target/arm: Export arm_v7m_mrs_control, Peter Maydell, 2023/03/06
- [PULL 15/21] target/arm: Handle m-profile in arm_is_secure, Peter Maydell, 2023/03/06
- [PULL 13/21] target/arm: Export arm_v7m_get_sp_ptr, Peter Maydell, 2023/03/06
- [PULL 17/21] target/arm: Diagnose incorrect usage of arm_is_secure subroutines, Peter Maydell, 2023/03/06
- [PULL 11/21] target/arm: Implement gdbstub pauth extension,
Peter Maydell <=
- [PULL 14/21] target/arm: Implement gdbstub m-profile systemreg and secext, Peter Maydell, 2023/03/06
- [PULL 16/21] target/arm: Stub arm_hcr_el2_eff for m-profile, Peter Maydell, 2023/03/06
- [PULL 21/21] hw: arm: allwinner-h3: Fix and complete H3 i2c devices, Peter Maydell, 2023/03/06
- [PULL 18/21] target/arm: Rewrite check_s2_mmu_setup, Peter Maydell, 2023/03/06
- [PULL 19/21] hw: arm: Support direct boot for Linux/arm64 EFI zboot images, Peter Maydell, 2023/03/06
- [PULL 20/21] hw: allwinner-i2c: Fix TWI_CNTR_INT_FLAG on SUN6i SoCs, Peter Maydell, 2023/03/06
- Re: [PULL 00/21] target-arm queue, Peter Maydell, 2023/03/07