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Re: [RESEND PATCH v6 3/8] hw/pci-bridge/cxl_root_port: Wire up AER
From: |
Fan Ni |
Subject: |
Re: [RESEND PATCH v6 3/8] hw/pci-bridge/cxl_root_port: Wire up AER |
Date: |
Mon, 6 Mar 2023 17:37:42 +0000 |
On Thu, Mar 02, 2023 at 01:37:04PM +0000, Jonathan Cameron wrote:
> We are missing necessary config write handling for AER emulation in
> the CXL root port. Add it based on pcie_root_port.c
>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> hw/pci-bridge/cxl_root_port.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
> index 6664783974..00195257f7 100644
> --- a/hw/pci-bridge/cxl_root_port.c
> +++ b/hw/pci-bridge/cxl_root_port.c
> @@ -187,12 +187,15 @@ static void cxl_rp_write_config(PCIDevice *d, uint32_t
> address, uint32_t val,
> int len)
> {
> uint16_t slt_ctl, slt_sta;
> + uint32_t root_cmd =
> + pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
>
> pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
> pci_bridge_write_config(d, address, val, len);
> pcie_cap_flr_write_config(d, address, val, len);
> pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
> pcie_aer_write_config(d, address, val, len);
> + pcie_aer_root_write_config(d, address, val, len, root_cmd);
>
> cxl_rp_dvsec_write_config(d, address, val, len);
> }
> --
> 2.37.2
>
>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
[RESEND PATCH v6 3/8] hw/pci-bridge/cxl_root_port: Wire up AER, Jonathan Cameron, 2023/03/02
- Message not available
- Re: [RESEND PATCH v6 3/8] hw/pci-bridge/cxl_root_port: Wire up AER,
Fan Ni <=
[RESEND PATCH v6 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI, Jonathan Cameron, 2023/03/02
[RESEND PATCH v6 5/8] hw/mem/cxl-type3: Add AER extended capability, Jonathan Cameron, 2023/03/02
[RESEND PATCH v6 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks, Jonathan Cameron, 2023/03/02
[RESEND PATCH v6 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use., Jonathan Cameron, 2023/03/02
[RESEND PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support., Jonathan Cameron, 2023/03/02