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[PULL 05/17] Hexagon (target/hexagon) Add overrides for callr
From: |
Taylor Simpson |
Subject: |
[PULL 05/17] Hexagon (target/hexagon) Add overrides for callr |
Date: |
Mon, 6 Mar 2023 21:34:26 -0800 |
Add overrides for
J2_callr
J2_callrt
J2_callrf
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-3-tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 6 ++++++
target/hexagon/macros.h | 12 +-----------
target/hexagon/genptr.c | 18 ++++++++++++++++++
3 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index f898f5b389..fb23d56d4a 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -589,11 +589,17 @@
#define fGEN_TCG_J2_call(SHORTCODE) \
gen_call(ctx, riV)
+#define fGEN_TCG_J2_callr(SHORTCODE) \
+ gen_callr(ctx, RsV)
#define fGEN_TCG_J2_callt(SHORTCODE) \
gen_cond_call(ctx, PuV, TCG_COND_EQ, riV)
#define fGEN_TCG_J2_callf(SHORTCODE) \
gen_cond_call(ctx, PuV, TCG_COND_NE, riV)
+#define fGEN_TCG_J2_callrt(SHORTCODE) \
+ gen_cond_callr(ctx, TCG_COND_EQ, PuV, RsV)
+#define fGEN_TCG_J2_callrf(SHORTCODE) \
+ gen_cond_callr(ctx, TCG_COND_NE, PuV, RsV)
#define fGEN_TCG_J2_endloop0(SHORTCODE) \
gen_endloop0(ctx)
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 17facadaad..6974ef6c9e 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -1,5 +1,5 @@
/*
- * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights
Reserved.
+ * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights
Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -415,16 +415,6 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,
int shift)
#define fBRANCH(LOC, TYPE) fWRITE_NPC(LOC)
#define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR)
#define fHINTJR(TARGET) { /* Not modelled in qemu */}
-#define fCALL(A) \
- do { \
- fWRITE_LR(fREAD_NPC()); \
- fBRANCH(A, COF_TYPE_CALL); \
- } while (0)
-#define fCALLR(A) \
- do { \
- fWRITE_LR(fREAD_NPC()); \
- fBRANCH(A, COF_TYPE_CALLR); \
- } while (0)
#define fWRITE_LOOP_REGS0(START, COUNT) \
do { \
WRITE_RREG(HEX_REG_LC0, COUNT); \
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 2bbe4e3a68..592438f61e 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -682,6 +682,13 @@ static void gen_call(DisasContext *ctx, int pc_off)
gen_write_new_pc_pcrel(ctx, pc_off, TCG_COND_ALWAYS, NULL);
}
+static void gen_callr(DisasContext *ctx, TCGv new_pc)
+{
+ TCGv next_PC = tcg_constant_tl(ctx->next_PC);
+ gen_log_reg_write(HEX_REG_LR, next_PC);
+ gen_write_new_pc_addr(ctx, new_pc, TCG_COND_ALWAYS, NULL);
+}
+
static void gen_cond_call(DisasContext *ctx, TCGv pred,
TCGCond cond, int pc_off)
{
@@ -697,6 +704,17 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred,
gen_set_label(skip);
}
+static void gen_cond_callr(DisasContext *ctx,
+ TCGCond cond, TCGv pred, TCGv new_pc)
+{
+ TCGv lsb = tcg_temp_new();
+ TCGLabel *skip = gen_new_label();
+ tcg_gen_andi_tl(lsb, pred, 1);
+ tcg_gen_brcondi_tl(cond, lsb, 0, skip);
+ gen_callr(ctx, new_pc);
+ gen_set_label(skip);
+}
+
static void gen_endloop0(DisasContext *ctx)
{
TCGv lpcfg = tcg_temp_new();
--
2.25.1
- [PULL 00/17] Hexagon (target/hexagon) updates, Taylor Simpson, 2023/03/07
- [PULL 13/17] Hexagon (tests/tcg/hexagon) Enable HVX tests, Taylor Simpson, 2023/03/07
- [PULL 04/17] Hexagon (target/hexagon) Add overrides for jumpr31 instructions, Taylor Simpson, 2023/03/07
- [PULL 10/17] Hexagon (target/hexagon) Analyze packet for HVX, Taylor Simpson, 2023/03/07
- [PULL 16/17] Hexagon (target/hexagon) Reduce manipulation of slot_cancelled, Taylor Simpson, 2023/03/07
- [PULL 05/17] Hexagon (target/hexagon) Add overrides for callr,
Taylor Simpson <=
- [PULL 09/17] Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not needed, Taylor Simpson, 2023/03/07
- [PULL 03/17] target/hexagon/idef-parser: Remove unused code paths, Taylor Simpson, 2023/03/07
- [PULL 17/17] Hexagon (target/hexagon) Improve code gen for predicated HVX instructions, Taylor Simpson, 2023/03/07
- [PULL 14/17] Hexagon (target/hexagon) Change subtract from zero to change sign, Taylor Simpson, 2023/03/07
- [PULL 02/17] target/hexagon/idef-parser: Elide mov in gen_pred_assign, Taylor Simpson, 2023/03/07
- [PULL 07/17] Hexagon (target/hexagon) Add overrides for dealloc-return instructions, Taylor Simpson, 2023/03/07
- [PULL 06/17] Hexagon (target/hexagon) Add overrides for endloop1/endloop01, Taylor Simpson, 2023/03/07
- [PULL 15/17] Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair], Taylor Simpson, 2023/03/07
- [PULL 01/17] Hexagon (target/hexagon) Restore --disable-hexagon-idef-parser build, Taylor Simpson, 2023/03/07
- [PULL 11/17] Hexagon (tests/tcg/hexagon) Update preg_alias.c, Taylor Simpson, 2023/03/07