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[PULL 06/20] target/mips: Set correct CP0.Config[4, 5] values for M14K(c
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 06/20] target/mips: Set correct CP0.Config[4, 5] values for M14K(c) |
Date: |
Wed, 8 Mar 2023 00:46:57 +0100 |
From: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230216051717.3911212-5-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/cpu-defs.c.inc | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index fdde04dfb9..d45f245a67 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -332,7 +332,10 @@ const mips_def_t mips_defs[] =
(0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1,
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
+ .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt) |
+ (1 << CP0C3_M),
+ .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
.CP0_Config7 = 1 << CP0C7_WII,
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
@@ -354,7 +357,10 @@ const mips_def_t mips_defs[] =
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
+ .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt) |
+ (1 << CP0C3_M),
+ .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),
+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),
.CP0_Config7 = 1 << CP0C7_WII,
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
--
2.38.1
- [PULL 00/20] MIPS patches for 2023-03-07, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 01/20] docs/system: Remove "mips" board from target-mips.rst, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 02/20] target/mips: Replace [g_]assert(0) -> g_assert_not_reached(), Philippe Mathieu-Daudé, 2023/03/07
- [PULL 03/20] target/mips: Fix JALS32/J32 instruction handling for microMIPS, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 04/20] target/mips: Fix SWM32 handling for microMIPS, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 05/20] target/mips: Implement CP0.Config7.WII bit support, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 06/20] target/mips: Set correct CP0.Config[4, 5] values for M14K(c),
Philippe Mathieu-Daudé <=
- [PULL 07/20] hw/mips: Declare all length properties as unsigned, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 08/20] hw/mips/itu: Pass SAAR using QOM link property, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 09/20] Revert "hw/isa/i82378: Remove intermediate IRQ forwarder", Philippe Mathieu-Daudé, 2023/03/07
- [PULL 10/20] Revert "hw/isa/vt82c686: Remove intermediate IRQ forwarder", Philippe Mathieu-Daudé, 2023/03/07
- [PULL 11/20] hw/display/sm501: Add debug property to control pixman usage, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 12/20] hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 13/20] hw/isa/vt82c686: Implement PCI IRQ routing, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 14/20] hw/ppc/pegasos2: Fix PCI interrupt routing, Philippe Mathieu-Daudé, 2023/03/07