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Re: [RESEND PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection
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From: |
Michael S. Tsirkin |
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Subject: |
Re: [RESEND PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support. |
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Date: |
Tue, 7 Mar 2023 20:34:02 -0500 |
On Tue, Mar 07, 2023 at 07:26:41PM +0000, Fan Ni wrote:
> > +typedef struct CXLError {
> > + QTAILQ_ENTRY(CXLError) node;
> > + int type; /* Error code as per FE definition */
> > + uint32_t header[32];
> Instead of using 32 here, would it be better to use
> CXL_RAS_ERR_HEADER_NUM?
merged as is, fix on top pls.
--
MST
- Re: [RESEND PATCH v6 4/8] hw/pci-bridge/cxl_root_port: Wire up MSI, (continued)
[RESEND PATCH v6 5/8] hw/mem/cxl-type3: Add AER extended capability, Jonathan Cameron, 2023/03/02
[RESEND PATCH v6 6/8] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks, Jonathan Cameron, 2023/03/02
[RESEND PATCH v6 7/8] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use., Jonathan Cameron, 2023/03/02
[RESEND PATCH v6 8/8] hw/mem/cxl_type3: Add CXL RAS Error Injection Support., Jonathan Cameron, 2023/03/02
Re: [RESEND PATCH v6 0/8] hw/cxl: RAS error emulation and injection, Michael S. Tsirkin, 2023/03/06