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[PATCH 08/45] target/riscv: Refactor some of the generic vector function
From: |
Lawrence Hunter |
Subject: |
[PATCH 08/45] target/riscv: Refactor some of the generic vector functionality |
Date: |
Fri, 10 Mar 2023 16:03:09 +0000 |
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Moves the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commit without check duplication.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
---
target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++--------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 4106bd6994..bb5e2c5407 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1187,9 +1187,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn
*gvec_fn,
gen_helper_gvec_4_ptr *fn)
{
TCGLabel *over = gen_new_label();
- if (!opivv_check(s, a)) {
- return false;
- }
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
@@ -1223,6 +1220,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
}; \
+ if (!opivv_check(s, a)) { \
+ return false; \
+ } \
return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
}
@@ -1282,10 +1282,6 @@ static inline bool
do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
gen_helper_opivx *fn)
{
- if (!opivx_check(s, a)) {
- return false;
- }
-
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
TCGv_i64 src1 = tcg_temp_new_i64();
@@ -1307,6 +1303,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
}; \
+ if (!opivx_check(s, a)) { \
+ return false; \
+ } \
return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
}
@@ -1439,10 +1438,6 @@ static inline bool
do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
gen_helper_opivx *fn, imm_mode_t imm_mode)
{
- if (!opivx_check(s, a)) {
- return false;
- }
-
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
@@ -1460,6 +1455,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
}; \
+ if (!opivx_check(s, a)) { \
+ return false; \
+ } \
return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \
fns[s->sew], IMM_MODE); \
}
@@ -1785,10 +1783,6 @@ static inline bool
do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
gen_helper_opivx *fn)
{
- if (!opivx_check(s, a)) {
- return false;
- }
-
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
TCGv_i32 src1 = tcg_temp_new_i32();
@@ -1810,7 +1804,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
}; \
- \
+ if (!opivx_check(s, a)) { \
+ return false; \
+ } \
return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
}
--
2.39.2
- [PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support, (continued)
- [PATCH 30/45] target/riscv: Add vsha2ms.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 00/45] Add RISC-V vector cryptographic instruction set support, Lawrence Hunter, 2023/03/10
- [PATCH 05/45] target/riscv: Add vclmul.vx decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 07/45] target/riscv: Add vclmulh.vx decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 09/45] qemu/bitops.h: Limit rotate amounts, Lawrence Hunter, 2023/03/10
- [PATCH 03/45] target/riscv: Add vclmul.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 01/45] target/riscv: Add zvkb cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 02/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 06/45] target/riscv: Add vclmulh.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 11/45] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/03/10
- [PATCH 08/45] target/riscv: Refactor some of the generic vector functionality,
Lawrence Hunter <=
- [PATCH 16/45] target/riscv: Add zvkned cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 19/45] target/riscv: Add vaesdf.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 22/45] target/riscv: Add vaesdm.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 18/45] target/riscv: Add vaesef.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 12/45] target/riscv: Add vbrev8.v decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 15/45] target/riscv: Expose zvkb cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 14/45] target/riscv: Add vandn.[vv, vx] decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 21/45] target/riscv: Add vaesdm.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 23/45] target/riscv: Add vaesz.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10