Re: [PATCH v5 2/2] target/riscv: redirect XVentanaCondOps to use the Zicond functions

[Alistair Francis]

On Wed, Mar 8, 2023 at 4:10 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> The Zicond standard extension implements the same instruction
> semantics as XVentanaCondOps, although using different mnemonics and
> opcodes.
>
> Point XVentanaCondOps to the (newly implemented) Zicond implementation
> to reduce the future maintenance burden.
>
> Also updating MAINTAINERS as trans_xventanacondops.c.inc.
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Don't downgrade to "Odd Fixes", but rather to "Maintained" (we are
>   not being paid to look after this, but will look after it
>   nonetheless).
>
> Changes in v2:
> - Calls into the gen_czero_{eqz,nez} helpers instead of calling
>   trans_czero_{eqz,nez} to bypass the require-check and ensure that
>   XVentanaCondOps can be enabled/disabled independently of Zicond.
>
>  MAINTAINERS                                    |  2 +-
>  .../insn_trans/trans_xventanacondops.c.inc     | 18 +++---------------
>  2 files changed, 4 insertions(+), 16 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 011fd85a09..1ad3c6fc9a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -311,7 +311,7 @@ F: target/riscv/xthead*.decode
>  RISC-V XVentanaCondOps extension
>  M: Philipp Tomsich <philipp.tomsich@vrull.eu>
>  L: qemu-riscv@nongnu.org
> -S: Supported
> +S: Maintained
>  F: target/riscv/XVentanaCondOps.decode
>  F: target/riscv/insn_trans/trans_xventanacondops.c.inc
>
> diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc 
> b/target/riscv/insn_trans/trans_xventanacondops.c.inc
> index 16849e6d4e..38c15f2825 100644
> --- a/target/riscv/insn_trans/trans_xventanacondops.c.inc
> +++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc
> @@ -1,7 +1,7 @@
>  /*
>   * RISC-V translation routines for the XVentanaCondOps extension.
>   *
> - * Copyright (c) 2021-2022 VRULL GmbH.
> + * Copyright (c) 2021-2023 VRULL GmbH.
>   *
>   * This program is free software; you can redistribute it and/or modify it
>   * under the terms and conditions of the GNU General Public License,
> @@ -16,24 +16,12 @@
>   * this program.  If not, see <http://www.gnu.org/licenses/>.
>   */
>
> -static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
> -{
> -    TCGv dest = dest_gpr(ctx, a->rd);
> -    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> -    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> -
> -    tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
> -
> -    gen_set_gpr(ctx, a->rd, dest);
> -    return true;
> -}
> -
>  static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
>  {
> -    return gen_vt_condmask(ctx, a, TCG_COND_NE);
> +    return gen_logic(ctx, a, gen_czero_eqz);
>  }
>
>  static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
>  {
> -    return gen_vt_condmask(ctx, a, TCG_COND_EQ);
> +    return gen_logic(ctx, a, gen_czero_nez);
>  }
> --
> 2.34.1
>
>