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[RFC PATCH v2 07/44] target/loongarch: Implement vneg
From: |
Song Gao |
Subject: |
[RFC PATCH v2 07/44] target/loongarch: Implement vneg |
Date: |
Tue, 28 Mar 2023 11:05:54 +0800 |
This patch includes;
- VNEG.{B/H/W/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 10 ++++++++++
target/loongarch/insn_trans/trans_lsx.c.inc | 20 ++++++++++++++++++++
target/loongarch/insns.decode | 7 +++++++
3 files changed, 37 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index c1960610c2..5eabb8c47a 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -802,6 +802,11 @@ static void output_vv_i(DisasContext *ctx, arg_vv_i *a,
const char *mnemonic)
output(ctx, mnemonic, "v%d, v%d, 0x%x", a->vd, a->vj, a->imm);
}
+static void output_vv(DisasContext *ctx, arg_vv *a, const char *mnemonic)
+{
+ output(ctx, mnemonic, "v%d, v%d", a->vd, a->vj);
+}
+
INSN_LSX(vadd_b, vvv)
INSN_LSX(vadd_h, vvv)
INSN_LSX(vadd_w, vvv)
@@ -821,3 +826,8 @@ INSN_LSX(vsubi_bu, vv_i)
INSN_LSX(vsubi_hu, vv_i)
INSN_LSX(vsubi_wu, vv_i)
INSN_LSX(vsubi_du, vv_i)
+
+INSN_LSX(vneg_b, vv)
+INSN_LSX(vneg_h, vv)
+INSN_LSX(vneg_w, vv)
+INSN_LSX(vneg_d, vv)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index 99a5c2474d..dc66e44a75 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -44,6 +44,21 @@ static bool gvec_vvv(DisasContext *ctx, arg_vvv *a, MemOp
mop,
return true;
}
+static bool gvec_vv(DisasContext *ctx, arg_vv *a, MemOp mop,
+ void (*func)(unsigned, uint32_t, uint32_t,
+ uint32_t, uint32_t))
+{
+ uint32_t dofs, jofs;
+
+ CHECK_SXE;
+
+ dofs = vreg_full_offset(a->vd);
+ jofs = vreg_full_offset(a->vj);
+
+ func(mop, dofs, jofs, 16, 16);
+ return true;
+}
+
static bool gvec_vv_i(DisasContext *ctx, arg_vv_i *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
int64_t, uint32_t, uint32_t))
@@ -91,3 +106,8 @@ TRANS(vsubi_bu, gvec_subi, MO_8)
TRANS(vsubi_hu, gvec_subi, MO_16)
TRANS(vsubi_wu, gvec_subi, MO_32)
TRANS(vsubi_du, gvec_subi, MO_64)
+
+TRANS(vneg_b, gvec_vv, MO_8, tcg_gen_gvec_neg)
+TRANS(vneg_h, gvec_vv, MO_16, tcg_gen_gvec_neg)
+TRANS(vneg_w, gvec_vv, MO_32, tcg_gen_gvec_neg)
+TRANS(vneg_d, gvec_vv, MO_64, tcg_gen_gvec_neg)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 2a98c14518..d90798be11 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -490,12 +490,14 @@ dbcl 0000 00000010 10101 ...............
@i15
# LSX Argument sets
#
+&vv vd vj
&vvv vd vj vk
&vv_i vd vj imm
#
# LSX Formats
#
+@vv .... ........ ..... ..... vj:5 vd:5 &vv
@vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv
@vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i
@@ -518,3 +520,8 @@ vsubi_bu 0111 00101000 11000 ..... ..... .....
@vv_ui5
vsubi_hu 0111 00101000 11001 ..... ..... ..... @vv_ui5
vsubi_wu 0111 00101000 11010 ..... ..... ..... @vv_ui5
vsubi_du 0111 00101000 11011 ..... ..... ..... @vv_ui5
+
+vneg_b 0111 00101001 11000 01100 ..... ..... @vv
+vneg_h 0111 00101001 11000 01101 ..... ..... @vv
+vneg_w 0111 00101001 11000 01110 ..... ..... @vv
+vneg_d 0111 00101001 11000 01111 ..... ..... @vv
--
2.31.1
- [RFC PATCH v2 00/44] Add LoongArch LSX instructions, Song Gao, 2023/03/27
- [RFC PATCH v2 04/44] target/loongarch: Add CHECK_SXE maccro for check LSX enable, Song Gao, 2023/03/27
- [RFC PATCH v2 02/44] target/loongarch: CPUCFG support LSX, Song Gao, 2023/03/27
- [RFC PATCH v2 07/44] target/loongarch: Implement vneg,
Song Gao <=
- [RFC PATCH v2 08/44] target/loongarch: Implement vsadd/vssub, Song Gao, 2023/03/27
- [RFC PATCH v2 06/44] target/loongarch: Implement vaddi/vsubi, Song Gao, 2023/03/27
- [RFC PATCH v2 03/44] target/loongarch: meson.build support build LSX, Song Gao, 2023/03/27
- [RFC PATCH v2 05/44] target/loongarch: Implement vadd/vsub, Song Gao, 2023/03/27