Re: [PATCH v2 6/6] target/ppc: Implement HEIR SPR

[Michael Neuling]

Nick,

> +    case POWERPC_EXCP_HV_EMU:
> +        env->spr[SPR_HEIR] = insn;
> +        if (is_prefix_excp(env, insn)) {
> +            uint32_t insn2 = ppc_ldl_code(env, env->nip + 4);
> +            env->spr[SPR_HEIR] |= (uint64_t)insn2 << 32;

Are inst and inst2 in the right locations here? I think you might need
insn in the top half and insn2 in the bottom.

I wrote the little test case below. I'd expect GPR0 and GPR1 to end up
with the same value, but they don't with this code

qemu correctly sees the bad prefix instruction as HSRR1[34] is set.

Mikey

% cat heir.S
#define SPR_HEIR        (0x153)
#define SPR_HSRR0       (0x13a)

start:
        . = 0x10
        .long (1<<26) | 0
        .long 0x0

        . = 0xe40
illegal:
        mfspr 0, SPR_HEIR
        mfspr 2, SPR_HSRR0
        ld    1, 0(2)
        b .

% powerpc64-linux-gnu-gcc -o heir.o -c heir.S
% powerpc64-linux-gnu-objcopy -O binary heir.o
heir.stripped
% qemu-system-ppc64 -nographic-machine powernv10 -cpu POWER10 -display none 
-vga none -m 1g -accel tcg  -serial mon:stdio -bios 
/home/mikey/devel/test/heir.stripped
QEMU 7.2.91 monitor - type 'help' for more information
(qemu) info registers

CPU#0
NIP 0000000000000e4c   LR 0000000000000000 CTR 0000000000000000 XER
0000000000000000 CPU#0
MSR 9000000000000000 HID0 0000000000000000  HF fc000006 iidx 7 didx 7
TB 00000000 2494783394 DECR 1800184060
GPR00 0000000004000000 0400000000000000 0000000000000010 0000000001000000
GPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000
CR 00000000  [ -  -  -  -  -  -  -  -  ]             RES ffffffffffffffff
FPR00 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR04 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR08 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR12 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR16 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR20 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR24 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPR28 0000000000000000 0000000000000000 0000000000000000 0000000000000000
FPSCR 0000000000000000
 SRR0 0000000000000000  SRR1 0000000000000000    PVR 0000000000800200 VRSAVE 
0000000000000000
SPRG0 0000000000000000 SPRG1 0000000000000000  SPRG2 0000000000000000  SPRG3 
0000000000000000
SPRG4 0000000000000000 SPRG5 0000000000000000  SPRG6 0000000000000000  SPRG7 
0000000000000000
HSRR0 0000000000000010 HSRR1 9000000020000000
 CFAR 0000000000000e4c
 LPCR 000000000000000c
 PTCR 0000000000000000   DAR 0000000000000000  DSISR 0000000000000000
(qemu)