Re: [PATCH v2 1/3] hw/riscv: add CVA6 machine

[Ben Dooks]

On 09/06/2025 12:24, Daniel Henrique Barboza wrote:
> On 5/27/25 8:24 AM, Ben Dooks wrote:
> > Add a (currently Genesy2 based) CVA6 machine.
> >
> > Has SPI and UART, the GPIO and Ethernet are currently black-holed
> > as there is no hardware model for them (lowRISC ethernet and Xilinx
> > GPIO)
> >
> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> > ---
> > v2:

Apologie,s looks like it this got rebased out of the release

> > +/* plic register interface in corev_apu/rv_plic/rtl/plic_regmap.sv */
> > +
>
> I believe you've missed my comment in v1:

would this be ok

/*
* plic register interface in corev_apu/rv_plic/rtl/plic_regmap.sv
* https://github.com/pulp-platform/rv_plic/blob/master/rtl/plic_regmap.sv
*/

--
Ben Dooks                               http://www.codethink.co.uk/
Senior Engineer                         Codethink - Providing Genius

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