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Re: [Qemu-ppc] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() argument t


From: Jia Liu
Subject: Re: [Qemu-ppc] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() argument to CPUState
Date: Wed, 4 Sep 2013 20:50:30 +0800

On Wed, Sep 4, 2013 at 5:05 PM, Andreas Färber <address@hidden> wrote:
> Signed-off-by: Andreas Färber <address@hidden>
> ---
>  cputlb.c                           |  6 +++---
>  exec.c                             |  4 +---
>  hw/sh4/sh7750.c                    |  2 +-
>  include/exec/exec-all.h            |  4 ++--
>  target-alpha/cpu.c                 |  2 +-
>  target-alpha/sys_helper.c          |  2 +-
>  target-arm/cpu.c                   |  2 +-
>  target-arm/helper.c                | 28 +++++++++++++++++-------
>  target-cris/cpu.c                  |  2 +-
>  target-i386/cpu.c                  |  2 +-
>  target-i386/helper.c               | 17 ++++++++++-----
>  target-i386/machine.c              |  2 +-
>  target-i386/svm_helper.c           |  2 +-
>  target-lm32/cpu.c                  |  2 +-
>  target-m68k/cpu.c                  |  2 +-
>  target-microblaze/cpu.c            |  2 +-
>  target-microblaze/mmu.c            |  2 +-
>  target-mips/cpu.c                  |  2 +-
>  target-mips/machine.c              |  3 ++-
>  target-mips/op_helper.c            |  4 +++-
>  target-moxie/cpu.c                 |  2 +-
>  target-openrisc/cpu.c              |  2 +-
>  target-openrisc/interrupt.c        |  2 +-
>  target-openrisc/interrupt_helper.c |  2 +-
>  target-openrisc/sys_helper.c       |  2 +-
>  target-ppc/excp_helper.c           |  4 ++--
>  target-ppc/helper_regs.h           |  2 +-
>  target-ppc/misc_helper.c           |  4 +++-
>  target-ppc/mmu-hash64.c            |  6 ++++--
>  target-ppc/mmu_helper.c            | 44 
> ++++++++++++++++++++++++--------------
>  target-ppc/translate_init.c        |  2 +-
>  target-s390x/cpu.c                 |  5 ++---
>  target-s390x/mem_helper.c          | 13 +++++++----
>  target-sh4/cpu.c                   |  2 +-
>  target-sh4/helper.c                |  2 +-
>  target-sparc/cpu.c                 |  2 +-
>  target-sparc/ldst_helper.c         | 16 ++++++++------
>  target-sparc/machine.c             |  3 ++-
>  target-unicore32/cpu.c             |  2 +-
>  target-unicore32/helper.c          |  4 +++-
>  target-xtensa/op_helper.c          |  4 +++-
>  41 files changed, 132 insertions(+), 85 deletions(-)
>
> diff --git a/cputlb.c b/cputlb.c
> index 817180e..bfa7417 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -52,9 +52,9 @@ static const CPUTLBEntry s_cputlb_empty_entry = {
>   * entries from the TLB at any time, so flushing more entries than
>   * required is only an efficiency issue, not a correctness issue.
>   */
> -void tlb_flush(CPUArchState *env, int flush_global)
> +void tlb_flush(CPUState *cpu, int flush_global)
>  {
> -    CPUState *cpu = ENV_GET_CPU(env);
> +    CPUArchState *env = cpu->env_ptr;
>      int i;
>
>  #if defined(DEBUG_TLB)
> @@ -107,7 +107,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
>                 VADDR_PRIx "/%" VADDR_PRIx ")\n",
>                 cpu->tlb_flush_addr, cpu->tlb_flush_mask);
>  #endif
> -        tlb_flush(env, 1);
> +        tlb_flush(cpu, 1);
>          return;
>      }
>      /* must reset current TB so that interrupts cannot modify the
> diff --git a/exec.c b/exec.c
> index 9210834..8e514e8 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -1720,9 +1720,7 @@ static void tcg_commit(MemoryListener *listener)
>         reset the modified entries */
>      /* XXX: slow ! */
>      CPU_FOREACH(cpu) {
> -        CPUArchState *env = cpu->env_ptr;
> -
> -        tlb_flush(env, 1);
> +        tlb_flush(cpu, 1);
>      }
>  }
>
> diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
> index 1439ba4..4a39357 100644
> --- a/hw/sh4/sh7750.c
> +++ b/hw/sh4/sh7750.c
> @@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
>      case SH7750_PTEH_A7:
>          /* If asid changes, clear all registered tlb entries. */
>          if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
> -            tlb_flush(&s->cpu->env, 1);
> +            tlb_flush(CPU(s->cpu), 1);
>          }
>          s->cpu->env.pteh = mem_value;
>          return;
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 550e58d..f2d1c6c 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -97,7 +97,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, 
> tb_page_addr_t end,
>  #if !defined(CONFIG_USER_ONLY)
>  /* cputlb.c */
>  void tlb_flush_page(CPUState *cpu, target_ulong addr);
> -void tlb_flush(CPUArchState *env, int flush_global);
> +void tlb_flush(CPUState *cpu, int flush_global);
>  void tlb_set_page(CPUState *cpu, target_ulong vaddr,
>                    hwaddr paddr, int prot,
>                    int mmu_idx, target_ulong size);
> @@ -107,7 +107,7 @@ static inline void tlb_flush_page(CPUState *cpu, 
> target_ulong addr)
>  {
>  }
>
> -static inline void tlb_flush(CPUArchState *env, int flush_global)
> +static inline void tlb_flush(CPUState *cpu, int flush_global)
>  {
>  }
>  #endif
> diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
> index 9931f9f..d839d53 100644
> --- a/target-alpha/cpu.c
> +++ b/target-alpha/cpu.c
> @@ -294,7 +294,7 @@ static void alpha_cpu_initfn(Object *obj)
>
>      cs->env_ptr = env;
>      cpu_exec_init(env);
> -    tlb_flush(env, 1);
> +    tlb_flush(cs, 1);
>
>      alpha_translate_init();
>
> diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
> index 5f7d7dd..187ccf7 100644
> --- a/target-alpha/sys_helper.c
> +++ b/target-alpha/sys_helper.c
> @@ -64,7 +64,7 @@ void helper_call_pal(CPUAlphaState *env, uint64_t pc, 
> uint64_t entry_ofs)
>
>  void helper_tbia(CPUAlphaState *env)
>  {
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(alpha_env_get_cpu(env)), 1);
>  }
>
>  void helper_tbis(CPUAlphaState *env, uint64_t p)
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index f9f6930..2a0e891 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -163,7 +163,7 @@ static void arm_cpu_reset(CPUState *s)
>                                &env->vfp.fp_status);
>      set_float_detect_tininess(float_tininess_before_rounding,
>                                &env->vfp.standard_fp_status);
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>      /* Reset is a state change for some CPUARMState fields which we
>       * bake assumptions about into translated code, so we need to
>       * tb_flush().
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 4daf82e..7c87ffa 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -270,18 +270,22 @@ void init_cpreg_list(ARMCPU *cpu)
>
>  static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t 
> value)
>  {
> +    ARMCPU *cpu = arm_env_get_cpu(env);
> +
>      env->cp15.c3 = value;
> -    tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
> +    tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
>      return 0;
>  }
>
>  static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t 
> value)
>  {
> +    ARMCPU *cpu = arm_env_get_cpu(env);
> +
>      if (env->cp15.c13_fcse != value) {
>          /* Unlike real hardware the qemu TLB uses virtual addresses,
>           * not modified virtual addresses, so this causes a TLB flush.
>           */
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>          env->cp15.c13_fcse = value;
>      }
>      return 0;
> @@ -289,12 +293,14 @@ static int fcse_write(CPUARMState *env, const 
> ARMCPRegInfo *ri, uint64_t value)
>  static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                              uint64_t value)
>  {
> +    ARMCPU *cpu = arm_env_get_cpu(env);
> +
>      if (env->cp15.c13_context != value && !arm_feature(env, 
> ARM_FEATURE_MPU)) {
>          /* For VMSA (when not using the LPAE long descriptor page table
>           * format) this register includes the ASID, so do a TLB flush.
>           * For PMSA it is purely a process ID and no action is needed.
>           */
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>      env->cp15.c13_context = value;
>      return 0;
> @@ -303,8 +309,10 @@ static int contextidr_write(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>  static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                           uint64_t value)
>  {
> +    ARMCPU *cpu = arm_env_get_cpu(env);
> +
>      /* Invalidate all (TLBIALL) */
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>      return 0;
>  }
>
> @@ -321,8 +329,10 @@ static int tlbimva_write(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>  static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                            uint64_t value)
>  {
> +    ARMCPU *cpu = arm_env_get_cpu(env);
> +
>      /* Invalidate by ASID (TLBIASID) */
> -    tlb_flush(env, value == 0);
> +    tlb_flush(CPU(cpu), value == 0);
>      return 0;
>  }
>
> @@ -1178,11 +1188,13 @@ static int vmsa_ttbcr_raw_write(CPUARMState *env, 
> const ARMCPRegInfo *ri,
>  static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                              uint64_t value)
>  {
> +    ARMCPU *cpu = arm_env_get_cpu(env);
> +
>      if (arm_feature(env, ARM_FEATURE_LPAE)) {
>          /* With LPAE the TTBCR could result in a change of ASID
>           * via the TTBCR.A1 bit, so do a TLB flush.
>           */
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>      return vmsa_ttbcr_raw_write(env, ri, value);
>  }
> @@ -1444,7 +1456,7 @@ static int ttbr064_write(CPUARMState *env, const 
> ARMCPRegInfo *ri,
>                           uint64_t value)
>  {
>      /* Writes to the 64 bit format TTBRs may change the ASID */
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(arm_env_get_cpu(env)), 1);
>      return ttbr064_raw_write(env, ri, value);
>  }
>
> @@ -1508,7 +1520,7 @@ static int sctlr_write(CPUARMState *env, const 
> ARMCPRegInfo *ri, uint64_t value)
>      env->cp15.c1_sys = value;
>      /* ??? Lots of these bits are not implemented.  */
>      /* This may enable/disable the MMU, so do a TLB flush.  */
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(arm_env_get_cpu(env)), 1);
>      return 0;
>  }
>
> diff --git a/target-cris/cpu.c b/target-cris/cpu.c
> index b229a10..b7dbd08 100644
> --- a/target-cris/cpu.c
> +++ b/target-cris/cpu.c
> @@ -71,7 +71,7 @@ static void cris_cpu_reset(CPUState *s)
>      vr = env->pregs[PR_VR];
>      memset(env, 0, offsetof(CPUCRISState, load_info));
>      env->pregs[PR_VR] = vr;
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>
>  #if defined(CONFIG_USER_ONLY)
>      /* start in user mode with interrupts enabled.  */
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 944c3d7..b08c367 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2330,7 +2330,7 @@ static void x86_cpu_reset(CPUState *s)
>
>      memset(env, 0, offsetof(CPUX86State, pat));
>
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>
>      env->old_exception = -1;
>
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index e0df092..ac21cc4 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -385,22 +385,25 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
>
>      a20_state = (a20_state != 0);
>      if (a20_state != ((env->a20_mask >> 20) & 1)) {
> +        CPUState *cs = CPU(cpu);
> +
>  #if defined(DEBUG_MMU)
>          printf("A20 update: a20=%d\n", a20_state);
>  #endif
>          /* if the cpu is currently executing code, we must unlink it and
>             all the potentially executing TB */
> -        cpu_interrupt(CPU(cpu), CPU_INTERRUPT_EXITTB);
> +        cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
>
>          /* when a20 is changed, all the MMU mappings are invalid, so
>             we must flush everything */
> -        tlb_flush(env, 1);
> +        tlb_flush(cs, 1);
>          env->a20_mask = ~(1 << 20) | (a20_state << 20);
>      }
>  }
>
>  void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
>  {
> +    X86CPU *cpu = x86_env_get_cpu(env);
>      int pe_state;
>
>  #if defined(DEBUG_MMU)
> @@ -408,7 +411,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t 
> new_cr0)
>  #endif
>      if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
>          (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>
>  #ifdef TARGET_X86_64
> @@ -444,24 +447,28 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t 
> new_cr0)
>     the PDPT */
>  void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
>  {
> +    X86CPU *cpu = x86_env_get_cpu(env);
> +
>      env->cr[3] = new_cr3;
>      if (env->cr[0] & CR0_PG_MASK) {
>  #if defined(DEBUG_MMU)
>          printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
>  #endif
> -        tlb_flush(env, 0);
> +        tlb_flush(CPU(cpu), 0);
>      }
>  }
>
>  void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
>  {
> +    X86CPU *cpu = x86_env_get_cpu(env);
> +
>  #if defined(DEBUG_MMU)
>      printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
>  #endif
>      if ((new_cr4 ^ env->cr[4]) &
>          (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
>           CR4_SMEP_MASK | CR4_SMAP_MASK)) {
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>      /* SSE handling */
>      if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
> diff --git a/target-i386/machine.c b/target-i386/machine.c
> index 54dd2ab..371c126 100644
> --- a/target-i386/machine.c
> +++ b/target-i386/machine.c
> @@ -310,7 +310,7 @@ static int cpu_post_load(void *opaque, int version_id)
>      for (i = 0; i < DR7_MAX_BP; i++) {
>          hw_breakpoint_insert(env, i);
>      }
> -    tlb_flush(env, 1);
> +    tlb_flush(cs, 1);
>
>      return 0;
>  }
> diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
> index 197269b..c8dd553 100644
> --- a/target-i386/svm_helper.c
> +++ b/target-i386/svm_helper.c
> @@ -265,7 +265,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int 
> next_eip_addend)
>          break;
>      case TLB_CONTROL_FLUSH_ALL_ASID:
>          /* FIXME: this is not 100% correct but should work for now */
> -        tlb_flush(env, 1);
> +        tlb_flush(cs, 1);
>          break;
>      }
>
> diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
> index 69bc6bb..2d04bae 100644
> --- a/target-lm32/cpu.c
> +++ b/target-lm32/cpu.c
> @@ -56,7 +56,7 @@ static void lm32_cpu_reset(CPUState *s)
>      /* reset cpu state */
>      memset(env, 0, offsetof(CPULM32State, eba));
>
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>  }
>
>  static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
> diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
> index b24120d..096de44 100644
> --- a/target-m68k/cpu.c
> +++ b/target-m68k/cpu.c
> @@ -78,7 +78,7 @@ static void m68k_cpu_reset(CPUState *s)
>      env->cc_op = CC_OP_FLAGS;
>      /* TODO: We should set PC from the interrupt vector.  */
>      env->pc = 0;
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>  }
>
>  /* CPU models */
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index d724b6e..5a5fa5b 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -75,7 +75,7 @@ static void mb_cpu_reset(CPUState *s)
>
>      memset(env, 0, sizeof(CPUMBState));
>      env->res_addr = RES_ADDR_NONE;
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>
>      /* Disable stack protector.  */
>      env->shr = ~0;
> diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
> index 5b768f2..d10146e 100644
> --- a/target-microblaze/mmu.c
> +++ b/target-microblaze/mmu.c
> @@ -253,7 +253,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
>              /* Changes to the zone protection reg flush the QEMU TLB.
>                 Fortunately, these are very uncommon.  */
>              if (v != env->mmu.regs[rn]) {
> -                tlb_flush(env, 1);
> +                tlb_flush(CPU(cpu), 1);
>              }
>              env->mmu.regs[rn] = v;
>              break;
> diff --git a/target-mips/cpu.c b/target-mips/cpu.c
> index 8f26d11..c322f9b 100644
> --- a/target-mips/cpu.c
> +++ b/target-mips/cpu.c
> @@ -102,7 +102,7 @@ static void mips_cpu_reset(CPUState *s)
>      mcc->parent_reset(s);
>
>      memset(env, 0, offsetof(CPUMIPSState, mvp));
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>
>      cpu_state_reset(env);
>  }
> diff --git a/target-mips/machine.c b/target-mips/machine.c
> index 23504ba..0a07db8 100644
> --- a/target-mips/machine.c
> +++ b/target-mips/machine.c
> @@ -191,6 +191,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
>  int cpu_load(QEMUFile *f, void *opaque, int version_id)
>  {
>      CPUMIPSState *env = opaque;
> +    MIPSCPU *cpu = mips_env_get_cpu(env);
>      int i;
>
>      if (version_id != 3)
> @@ -303,6 +304,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
>          load_fpu(f, &env->fpus[i]);
>
>      /* XXX: ensure compatibility for halted bit ? */
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>      return 0;
>  }
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 14f727f..04fa7a2 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -1775,8 +1775,10 @@ target_ulong helper_yield(CPUMIPSState *env, 
> target_ulong arg)
>  /* TLB management */
>  static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
>  {
> +    MIPSCPU *cpu = mips_env_get_cpu(env);
> +
>      /* Flush qemu's TLB and discard all shadowed entries.  */
> -    tlb_flush (env, flush_global);
> +    tlb_flush(CPU(cpu), flush_global);
>      env->tlb->tlb_in_use = env->tlb->nb_tlb;
>  }
>
> diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
> index f7d1e6c..708501e 100644
> --- a/target-moxie/cpu.c
> +++ b/target-moxie/cpu.c
> @@ -55,7 +55,7 @@ static void moxie_cpu_reset(CPUState *s)
>      memset(env, 0, sizeof(CPUMoxieState));
>      env->pc = 0x1000;
>
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>  }
>
>  static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
> index 3eae4e9..04dd8eb 100644
> --- a/target-openrisc/cpu.c
> +++ b/target-openrisc/cpu.c
> @@ -68,7 +68,7 @@ static void openrisc_cpu_reset(CPUState *s)
>      memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
>  #endif
>
> -    tlb_flush(&cpu->env, 1);
> +    tlb_flush(s, 1);
>      /*tb_flush(&cpu->env);    FIXME: Do we need it?  */
>
>      cpu->env.pc = 0x100;
> diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
> index 52bcc6e..062e205 100644
> --- a/target-openrisc/interrupt.c
> +++ b/target-openrisc/interrupt.c
> @@ -55,7 +55,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
>
>      /* For machine-state changed between user-mode and supervisor mode,
>         we need flush TLB when we enter&exit EXCP.  */
> -    tlb_flush(env, 1);
> +    tlb_flush(cs, 1);
>
>      env->esr = env->sr;
>      env->sr &= ~SR_DME;
> diff --git a/target-openrisc/interrupt_helper.c 
> b/target-openrisc/interrupt_helper.c
> index 844648f..8194057 100644
> --- a/target-openrisc/interrupt_helper.c
> +++ b/target-openrisc/interrupt_helper.c
> @@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
>      }
>
>      if (need_flush_tlb) {
> -        tlb_flush(&cpu->env, 1);
> +        tlb_flush(cs, 1);
>      }
>  #endif
>      cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
> diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
> index 8f07f78..677f2d7 100644
> --- a/target-openrisc/sys_helper.c
> +++ b/target-openrisc/sys_helper.c
> @@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
>      case TO_SPR(0, 17): /* SR */
>          if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
>              (rb & (SR_IME | SR_DME | SR_SM))) {
> -            tlb_flush(env, 1);
> +            tlb_flush(cs, 1);
>          }
>          env->sr = rb;
>          env->sr |= SR_FO;      /* FO is const equal to 1 */
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index ef67b0e..449e78a 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -609,7 +609,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int 
> excp_model, int excp)
>      }
>      /* If we disactivated any translation, flush TLBs */
>      if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
> -        tlb_flush(env, 1);
> +        tlb_flush(cs, 1);
>      }
>
>  #ifdef TARGET_PPC64
> @@ -664,7 +664,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int 
> excp_model, int excp)
>          /* XXX: The BookE changes address space when switching modes,
>                  we should probably implement that as different MMU indexes,
>                  but for the moment we do it the slow way and flush all.  */
> -        tlb_flush(env, 1);
> +        tlb_flush(cs, 1);
>      }
>  }
>
> diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
> index a6d5e2f..a09bf03 100644
> --- a/target-ppc/helper_regs.h
> +++ b/target-ppc/helper_regs.h
> @@ -83,7 +83,7 @@ static inline int hreg_store_msr(CPUPPCState *env, 
> target_ulong value,
>      if (((value >> MSR_IR) & 1) != msr_ir ||
>          ((value >> MSR_DR) & 1) != msr_dr) {
>          /* Flush all tlb when changing translation mode */
> -        tlb_flush(env, 1);
> +        tlb_flush(cs, 1);
>          excp = POWERPC_EXCP_NONE;
>          cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
>      }
> diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
> index 616aab6..d04dafd 100644
> --- a/target-ppc/misc_helper.c
> +++ b/target-ppc/misc_helper.c
> @@ -60,10 +60,12 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong 
> val)
>
>  void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
>      if (likely(env->pb[num] != value)) {
>          env->pb[num] = value;
>          /* Should be optimized */
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>  }
>
> diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> index b060e69..74e8ffb 100644
> --- a/target-ppc/mmu-hash64.c
> +++ b/target-ppc/mmu-hash64.c
> @@ -94,6 +94,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, 
> CPUPPCState *env)
>
>  void helper_slbia(CPUPPCState *env)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>      int n, do_invalidate;
>
>      do_invalidate = 0;
> @@ -111,12 +112,13 @@ void helper_slbia(CPUPPCState *env)
>          }
>      }
>      if (do_invalidate) {
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>  }
>
>  void helper_slbie(CPUPPCState *env, target_ulong addr)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>      ppc_slb_t *slb;
>
>      slb = slb_lookup(env, addr);
> @@ -131,7 +133,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
>           *      and we still don't have a tlb_flush_mask(env, n, mask)
>           *      in QEMU, we just invalidate all TLBs
>           */
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>  }
>
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index cf652b7..b0db1ce 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -231,6 +231,7 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, 
> target_ulong eaddr,
>
>  static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>      ppc6xx_tlb_t *tlb;
>      int nr, max;
>
> @@ -244,7 +245,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState 
> *env)
>          tlb = &env->tlb.tlb6[nr];
>          pte_invalidate(&tlb->pte0);
>      }
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>  }
>
>  static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
> @@ -644,6 +645,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, 
> target_ulong address,
>  /* Helpers specific to PowerPC 40x implementations */
>  static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>      ppcemb_tlb_t *tlb;
>      int i;
>
> @@ -651,7 +653,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState 
> *env)
>          tlb = &env->tlb.tlbe[i];
>          tlb->prot &= ~PAGE_VALID;
>      }
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>  }
>
>  static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
> @@ -862,6 +864,7 @@ static int mmubooke_get_physical_address(CPUPPCState 
> *env, mmu_ctx_t *ctx,
>  static void booke206_flush_tlb(CPUPPCState *env, int flags,
>                                 const int check_iprot)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>      int tlb_size;
>      int i, j;
>      ppcmas_tlb_t *tlb = env->tlb.tlbm;
> @@ -878,7 +881,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int 
> flags,
>          tlb += booke206_tlb_size(env, i);
>      }
>
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>  }
>
>  static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
> @@ -1918,7 +1921,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
>          cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
>          break;
>      case POWERPC_MMU_BOOKE:
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>          break;
>      case POWERPC_MMU_BOOKE206:
>          booke206_flush_tlb(env, -1, 0);
> @@ -1931,7 +1934,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
>      case POWERPC_MMU_2_06a:
>      case POWERPC_MMU_2_06d:
>  #endif /* defined(TARGET_PPC64) */
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>          break;
>      default:
>          /* XXX: TODO */
> @@ -2009,7 +2012,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, 
> target_ulong addr)
>           *      and we still don't have a tlb_flush_mask(env, n, mask) in 
> QEMU,
>           *      we just invalidate all TLBs
>           */
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>          break;
>  #endif /* defined(TARGET_PPC64) */
>      default:
> @@ -2026,6 +2029,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, 
> target_ulong addr)
>  /* Special registers manipulation */
>  void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
>      LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
>      if (env->spr[SPR_SDR1] != value) {
>          env->spr[SPR_SDR1] = value;
> @@ -2047,7 +2052,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong 
> value)
>              env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF;
>              env->htab_base = value & SDR_32_HTABORG;
>          }
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>  }
>
> @@ -2065,6 +2070,8 @@ target_ulong helper_load_sr(CPUPPCState *env, 
> target_ulong sr_num)
>
>  void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong 
> value)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
>      LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
>              (int)srnum, value, env->sr[srnum]);
>  #if defined(TARGET_PPC64)
> @@ -2097,11 +2104,11 @@ void helper_store_sr(CPUPPCState *env, target_ulong 
> srnum, target_ulong value)
>              page = (16 << 20) * srnum;
>              end = page + (16 << 20);
>              for (; page != end; page += TARGET_PAGE_SIZE) {
> -                tlb_flush_page(env, page);
> +                tlb_flush_page(CPU(cpu), page);
>              }
>          }
>  #else
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>  #endif
>      }
>  }
> @@ -2423,6 +2430,7 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, 
> target_ulong address)
>  void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
>                        target_ulong value)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>      ppcemb_tlb_t *tlb;
>      target_ulong EPN, RPN, size;
>      int do_flush_tlbs;
> @@ -2458,13 +2466,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t 
> word, target_ulong entry,
>          }
>          tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
>          if (do_flush_tlbs) {
> -            tlb_flush(env, 1);
> +            tlb_flush(CPU(cpu), 1);
>          }
>          break;
>      case 1:
>          RPN = value & 0xFFFFFC0F;
>          if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) {
> -            tlb_flush(env, 1);
> +            tlb_flush(CPU(cpu), 1);
>          }
>          tlb->RPN = RPN;
>          break;
> @@ -2576,9 +2584,11 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
>
>  void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
>      env->spr[pidn] = pid;
>      /* changing PIDs mean we're in a different address space now */
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>  }
>
>  void helper_booke206_tlbwe(CPUPPCState *env)
> @@ -2673,7 +2683,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
>      if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
>          tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
>      } else {
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>  }
>
> @@ -2797,7 +2807,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, 
> target_ulong address)
>      if (address & 0x8) {
>          /* flush TLB1 entries */
>          booke206_invalidate_ea_tlb(env, 1, address);
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      } else {
>          /* flush TLB0 entries */
>          booke206_invalidate_ea_tlb(env, 0, address);
> @@ -2813,6 +2823,7 @@ void helper_booke206_tlbilx0(CPUPPCState *env, 
> target_ulong address)
>
>  void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>      int i, j;
>      int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
>      ppcmas_tlb_t *tlb = env->tlb.tlbm;
> @@ -2829,11 +2840,12 @@ void helper_booke206_tlbilx1(CPUPPCState *env, 
> target_ulong address)
>          }
>          tlb += booke206_tlb_size(env, i);
>      }
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>  }
>
>  void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
>  {
> +    PowerPCCPU *cpu = ppc_env_get_cpu(env);
>      int i, j;
>      ppcmas_tlb_t *tlb;
>      int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
> @@ -2869,7 +2881,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, 
> target_ulong address)
>              tlb->mas1 &= ~MAS1_VALID;
>          }
>      }
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>  }
>
>  void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 1df82c5..eb8b7e7 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8521,7 +8521,7 @@ static void ppc_cpu_reset(CPUState *s)
>  #endif /* TARGET_PPC64 */
>
>      /* Flush all TLBs */
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>  }
>
>  static void ppc_cpu_initfn(Object *obj)
> diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
> index d9b8470..608df5e 100644
> --- a/target-s390x/cpu.c
> +++ b/target-s390x/cpu.c
> @@ -113,14 +113,13 @@ static void s390_cpu_reset(CPUState *s)
>  {
>      S390CPU *cpu = S390_CPU(s);
>      S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
> -    CPUS390XState *env = &cpu->env;
>
>      s390_del_running_cpu(cpu);
>      scc->parent_reset(s);
>  #if !defined(CONFIG_USER_ONLY)
>      s->halted = 1;
>  #endif
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>  }
>
>  /* S390CPUClass::initial_reset() */
> @@ -161,7 +160,7 @@ static void s390_cpu_full_reset(CPUState *s)
>  #if !defined(CONFIG_USER_ONLY)
>      s->halted = 1;
>  #endif
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>  }
>
>  #if !defined(CONFIG_USER_ONLY)
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index 6bff6cc..bae6a5b 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -810,6 +810,7 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, 
> uint64_t array,
>  #if !defined(CONFIG_USER_ONLY)
>  void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
>  {
> +    S390CPU *cpu = s390_env_get_cpu(env);
>      int i;
>      uint64_t src = a2;
>
> @@ -824,11 +825,12 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, 
> uint64_t a2, uint32_t r3)
>          }
>      }
>
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>  }
>
>  void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
>  {
> +    S390CPU *cpu = s390_env_get_cpu(env);
>      int i;
>      uint64_t src = a2;
>
> @@ -842,7 +844,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, 
> uint64_t a2, uint32_t r3)
>          }
>      }
>
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>  }
>
>  void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> @@ -935,6 +937,7 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)
>  /* compare and swap and purge */
>  uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
>  {
> +    S390CPU *cpu = s390_env_get_cpu(env);
>      uint32_t cc;
>      uint32_t o1 = env->regs[r1];
>      uint64_t a2 = r2 & ~3ULL;
> @@ -944,7 +947,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, 
> uint64_t r2)
>          cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]);
>          if (r2 & 0x3) {
>              /* flush TLB / ALB */
> -            tlb_flush(env, 1);
> +            tlb_flush(CPU(cpu), 1);
>          }
>          cc = 0;
>      } else {
> @@ -1039,7 +1042,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t 
> pte_addr, uint64_t vaddr)
>  /* flush local tlb */
>  void HELPER(ptlb)(CPUS390XState *env)
>  {
> -    tlb_flush(env, 1);
> +    S390CPU *cpu = s390_env_get_cpu(env);
> +
> +    tlb_flush(CPU(cpu), 1);
>  }
>
>  /* store using real address */
> diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
> index fb176bf..05720f1 100644
> --- a/target-sh4/cpu.c
> +++ b/target-sh4/cpu.c
> @@ -77,7 +77,7 @@ static void superh_cpu_reset(CPUState *s)
>      scc->parent_reset(s);
>
>      memset(env, 0, offsetof(CPUSH4State, id));
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>
>      env->pc = 0xA0000000;
>  #if defined(CONFIG_USER_ONLY)
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index c56e543..9ebdd5c 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -585,7 +585,7 @@ void cpu_load_tlb(CPUSH4State * env)
>          entry->v = 0;
>      }
>
> -    tlb_flush(s, 1);
> +    tlb_flush(CPU(sh_env_get_cpu(s)), 1);
>  }
>
>  uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> index 6c1ff68..e1f6e61 100644
> --- a/target-sparc/cpu.c
> +++ b/target-sparc/cpu.c
> @@ -33,7 +33,7 @@ static void sparc_cpu_reset(CPUState *s)
>      scc->parent_reset(s);
>
>      memset(env, 0, offsetof(CPUSPARCState, version));
> -    tlb_flush(env, 1);
> +    tlb_flush(s, 1);
>      env->cwp = 0;
>  #ifndef TARGET_SPARC64
>      env->wim = 1;
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index 44c54f1..bf75ceb 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -865,7 +865,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, 
> uint64_t val, int asi,
>              case 2: /* flush region (16M) */
>              case 3: /* flush context (4G) */
>              case 4: /* flush entire */
> -                tlb_flush(env, 1);
> +                tlb_flush(CPU(cpu), 1);
>                  break;
>              default:
>                  break;
> @@ -890,7 +890,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, 
> uint64_t val, int asi,
>                     disabled mode are invalid in normal mode */
>                  if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
>                      (env->mmuregs[reg] & (MMU_E | MMU_NF | 
> env->def->mmu_bm))) {
> -                    tlb_flush(env, 1);
> +                    tlb_flush(CPU(cpu), 1);
>                  }
>                  break;
>              case 1: /* Context Table Pointer Register */
> @@ -901,7 +901,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, 
> uint64_t val, int asi,
>                  if (oldreg != env->mmuregs[reg]) {
>                      /* we flush when the MMU context changes because
>                         QEMU has no MMU context support */
> -                    tlb_flush(env, 1);
> +                    tlb_flush(CPU(cpu), 1);
>                  }
>                  break;
>              case 3: /* Synchronous Fault Status Register with Clear */
> @@ -1657,6 +1657,8 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong 
> addr, int asi, int size,
>  void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
>                     int asi, int size)
>  {
> +    SPARCCPU *cpu = sparc_env_get_cpu(env);
> +
>  #ifdef DEBUG_ASI
>      dump_asi("write", addr, asi, size, val);
>  #endif
> @@ -1865,7 +1867,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong 
> addr, target_ulong val,
>  #ifdef DEBUG_MMU
>                  dump_mmu(stdout, fprintf, env);
>  #endif
> -                tlb_flush(env, 1);
> +                tlb_flush(CPU(cpu), 1);
>              }
>              return;
>          }
> @@ -1954,13 +1956,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong 
> addr, target_ulong val,
>                  env->dmmu.mmu_primary_context = val;
>                  /* can be optimized to only flush MMU_USER_IDX
>                     and MMU_KERNEL_IDX entries */
> -                tlb_flush(env, 1);
> +                tlb_flush(CPU(cpu), 1);
>                  break;
>              case 2: /* Secondary context */
>                  env->dmmu.mmu_secondary_context = val;
>                  /* can be optimized to only flush MMU_USER_SECONDARY_IDX
>                     and MMU_KERNEL_SECONDARY_IDX entries */
> -                tlb_flush(env, 1);
> +                tlb_flush(CPU(cpu), 1);
>                  break;
>              case 5: /* TSB access */
>                  DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
> @@ -2389,7 +2391,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr 
> addr,
>      /* flush neverland mappings created during no-fault mode,
>         so the sequential MMU faults report proper fault types */
>      if (env->mmuregs[0] & MMU_NF) {
> -        tlb_flush(env, 1);
> +        tlb_flush(cs, 1);
>      }
>  }
>  #else
> diff --git a/target-sparc/machine.c b/target-sparc/machine.c
> index a353dab..3f3de4c 100644
> --- a/target-sparc/machine.c
> +++ b/target-sparc/machine.c
> @@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque)
>  int cpu_load(QEMUFile *f, void *opaque, int version_id)
>  {
>      CPUSPARCState *env = opaque;
> +    SPARCCPU *cpu = sparc_env_get_cpu(env);
>      int i;
>      uint32_t tmp;
>
> @@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
>      qemu_get_be64s(f, &env->ssr);
>      cpu_get_timer(f, env->hstick);
>  #endif
> -    tlb_flush(env, 1);
> +    tlb_flush(CPU(cpu), 1);
>      return 0;
>  }
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> index dcf3b16..a317217 100644
> --- a/target-unicore32/cpu.c
> +++ b/target-unicore32/cpu.c
> @@ -141,7 +141,7 @@ static void uc32_cpu_initfn(Object *obj)
>      env->regs[31] = 0x03000000;
>  #endif
>
> -    tlb_flush(env, 1);
> +    tlb_flush(cs, 1);
>
>      if (tcg_enabled() && !inited) {
>          inited = true;
> diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
> index f91ed93..8de6a33 100644
> --- a/target-unicore32/helper.c
> +++ b/target-unicore32/helper.c
> @@ -57,6 +57,8 @@ uint32_t HELPER(clz)(uint32_t x)
>  void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
>          uint32_t cop)
>  {
> +    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
>      /*
>       * movc pp.nn, rn, #imm9
>       *      rn: UCOP_REG_D
> @@ -125,7 +127,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, 
> uint32_t creg,
>      case 6:
>          if ((cop <= 6) && (cop >= 2)) {
>              /* invalid all tlb */
> -            tlb_flush(env, 1);
> +            tlb_flush(CPU(cpu), 1);
>              return;
>          }
>          break;
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 5771841..70937b6 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -479,10 +479,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env, 
> uint32_t pc, uint32_t vaddr)
>
>  void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
>  {
> +    XtensaCPU *cpu = xtensa_env_get_cpu(env);
> +
>      v = (v & 0xffffff00) | 0x1;
>      if (v != env->sregs[RASID]) {
>          env->sregs[RASID] = v;
> -        tlb_flush(env, 1);
> +        tlb_flush(CPU(cpu), 1);
>      }
>  }

target-openrisc: Tested-by: Jia Liu <address@hidden>

>
> --
> 1.8.1.4
>



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