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[Qemu-ppc] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx |
Date: |
Fri, 7 Mar 2014 00:32:44 +0100 |
From: Tom Musta <address@hidden>
This patch refactors the stxsdx instruction. Reusable code is
extracted into a macro which will be used in subsequent patches
in this series.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 27 +++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 18ff8f7..2dfdf6c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7112,20 +7112,23 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_temp_free_i64(tmp);
}
-static void gen_stxsdx(DisasContext *ctx)
-{
- TCGv EA;
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- gen_set_access_type(ctx, ACCESS_INT);
- EA = tcg_temp_new();
- gen_addr_reg_index(ctx, EA);
- gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
- tcg_temp_free(EA);
+#define VSX_STORE_SCALAR(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_reg_index(ctx, EA); \
+ gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
+ tcg_temp_free(EA); \
}
+VSX_STORE_SCALAR(stxsdx, st64)
+
static void gen_stxvd2x(DisasContext *ctx)
{
TCGv EA;
--
1.8.1.4
- [Qemu-ppc] [PULL 033/130] target-ppc: Add VSX Rounding Instructions, (continued)
- [Qemu-ppc] [PULL 033/130] target-ppc: Add VSX Rounding Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 043/130] target-ppc: VSX Stage 4: Add xssqrtsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 056/130] target-ppc: Add ISA 2.06 divweu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 047/130] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 041/130] target-ppc: VSX Stage 4: Add xsdivsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 023/130] target-ppc: Add VSX ISA2.06 xsqrt Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 022/130] target-ppc: Add VSX ISA2.06 xre Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 038/130] target-ppc: VSX Stage 4: Add stxsiwx and stxsspx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 049/130] target-ppc: Floating Merge Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 119/130] spapr-vlan: flush queue whenever can_receive can go from false to true, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 037/130] target-ppc: VSX Stage 4: Refactor stxsdx,
Alexander Graf <=
- [Qemu-ppc] [PULL 034/130] target-ppc: VSX Stage 4: Add VSX 2.07 Flag, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 036/130] target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 024/130] target-ppc: Add VSX ISA2.06 xrsqrte Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 008/130] kvm: Add a new machine option kvm-type, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 013/130] PPC: KVM: add support for LPCR, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 130/130] target-ppc: spapr: e500: fix to use cpu_dt_id, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 113/130] target-ppc: Altivec 2.07: Vector Gather Bits by Bytes, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 115/130] target-ppc: Altivec 2.07: Binary Coded Decimal Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 118/130] target-ppc: Altivec 2.07: Vector Permute and Exclusive OR, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 099/130] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers, Alexander Graf, 2014/03/06