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[Qemu-ppc] [V2 PATCH 14/37] target-ppc: Introduce Decoder Macros for DFP
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [V2 PATCH 14/37] target-ppc: Introduce Decoder Macros for DFP |
Date: |
Mon, 21 Apr 2014 15:54:58 -0500 |
Add decoder macros for the various Decimal Floating Point
instruction forms. Illegal instruction masks are used to not only
guard against reserved instruction field use, but also to catch
illegal quad word forms that use odd-numbered floating point registers.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/translate.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 109 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index abbab1f..12aee63 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11176,6 +11176,115 @@ GEN_XXSEL_ROW(0x1F)
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
+#undef GEN_DFP_T_A_B_Rc
+#undef GEN_DFP_BF_A_B
+#undef GEN_DFP_BF_A_DCM
+#undef GEN_DFP_T_B_U32_U32_Rc
+#undef GEN_DFP_T_A_B_I32_Rc
+#undef GEN_DFP_T_B_Rc
+#undef GEN_DFP_T_FPR_I32_Rc
+
+#define _GEN_DFP_LONG(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_LONGx2(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_LONGx4(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_QUAD(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_QUADx2(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
+
+#define _GEN_DFP_QUADx4(name, op1, op2, mask) \
+GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
+GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
+
+#define GEN_DFP_T_A_B_Rc(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x00000000)
+
+#define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00210800)
+
+#define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00200800)
+
+#define GEN_DFP_T_B_Rc(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x001F0000)
+
+#define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
+
+#define GEN_DFP_Tp_B_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
+
+#define GEN_DFP_T_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
+
+#define GEN_DFP_BF_A_B(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x00000001)
+
+#define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00610801)
+
+#define GEN_DFP_BF_A_Bp(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00600801)
+
+#define GEN_DFP_BF_A_DCM(name, op1, op2) \
+_GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
+
+#define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
+_GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
+
+#define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
+_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
+
+#define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
+_GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
+
+#define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
+_GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
+
+#define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
+_GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
+
+#define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
+_GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
+
+#define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
+_GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
+
+#define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
+_GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
+
+#define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x00070000)
+
+#define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x00270800)
+
+#define GEN_DFP_S_T_B_Rc(name, op1, op2) \
+_GEN_DFP_LONG(name, op1, op2, 0x000F0000)
+
+#define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
+_GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
+
+#define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
+_GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
+
+#define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
+_GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
+
#undef GEN_SPE
#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type,
PPC_NONE)
--
1.7.1
- [Qemu-ppc] [V2 PATCH 03/37] libdecnumber: Prepare libdecnumber for QEMU include structure, (continued)
- [Qemu-ppc] [V2 PATCH 03/37] libdecnumber: Prepare libdecnumber for QEMU include structure, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 07/37] libdecnumber: Eliminate Unused Variable in decSetSubnormal, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 15/37] target-ppc: Introduce DFP Helper Utilities, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 04/37] libdecnumber: Modify dconfig.h to Integrate with QEMU, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 08/37] target-ppc: Enable Building of libdecnumber, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 09/37] libdecnumber: Introduce decNumberFrom[U]Int64, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 10/37] libdecnumber: Introduce decNumberIntegralToInt64, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 12/37] target-ppc: Define FPR Pointer Type for Helpers, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 11/37] libdecnumber: Fix decNumberSetBCD, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 13/37] target-ppc: Introduce Generator Macros for DFP Arithmetic Forms, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 14/37] target-ppc: Introduce Decoder Macros for DFP,
Tom Musta <=
- [Qemu-ppc] [V2 PATCH 16/37] target-ppc: Introduce DFP Post Processor Utilities, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 17/37] target-ppc: Introduce DFP Add, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 18/37] target-ppc: Introduce DFP Subtract, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 19/37] target-ppc: Introduce DFP Multiply, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 20/37] target-ppc: Introduce DFP Divide, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 28/37] target-ppc: Introduce DFP Round to Integer, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 29/37] target-ppc: Introduce DFP Convert to Long/Extended, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 30/37] target-ppc: Introduce Round to DFP Short/Long, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 32/37] target-ppc: Introduce DFP Convert to Fixed, Tom Musta, 2014/04/21
- [Qemu-ppc] [V2 PATCH 33/37] target-ppc: Introduce DFP Decode DPD to BCD, Tom Musta, 2014/04/21