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[Qemu-ppc] [PATCH 8/9] target-ppc: Introduce tcheck
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [PATCH 8/9] target-ppc: Introduce tcheck |
Date: |
Thu, 18 Dec 2014 10:34:36 -0600 |
Add a degenerate implementation of the Transaction Check (tcheck)
instruction. Since transaction always immediately fail, this
implementation simply sets CR[BF] to 0b1000, i.e. TDOOMED = 1
and MSR[TS] == 0.
Signed-off-by: Tom Musta <address@hidden>
---
target-ppc/translate.c | 17 +++++++++++++++++
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f468a5d..a3c79a6 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9676,6 +9676,21 @@ GEN_TM_NOOP(tabortdc);
GEN_TM_NOOP(tabortdci);
GEN_TM_NOOP(tsr);
+static void gen_tcheck(DisasContext *ctx)
+{
+ if (unlikely(!ctx->tm_enabled)) {
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
+ return;
+ }
+ /* Because tbegin always fails, the tcheck implementation
+ * is simple:
+ *
+ * CR[CRF] = TDOOMED || MSR[TS] || 0b0
+ * = 0b1 || 0b00 || 0b0
+ */
+ tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
+}
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -11105,6 +11120,8 @@ GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E,
0x1B, 0x00000000, \
PPC_NONE, PPC2_TM),
GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
PPC_NONE, PPC2_TM),
+GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
+ PPC_NONE, PPC2_TM),
};
#include "helper_regs.h"
--
1.7.1
- [Qemu-ppc] [PATCH 3/9] target-ppc: Introduce tm_enabled Bit to CPU State, (continued)
[Qemu-ppc] [PATCH 6/9] target-ppc: Introduce tbegin, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 7/9] target-ppc: Introduce TM Noops, Tom Musta, 2014/12/18
[Qemu-ppc] [PATCH 8/9] target-ppc: Introduce tcheck,
Tom Musta <=
[Qemu-ppc] [PATCH 9/9] target-ppc: Introduce Privileged TM Noops, Tom Musta, 2014/12/18
Re: [Qemu-ppc] [PATCH 0/9] target-ppc: Rudimentary Support for Transactional Memory, Alexander Graf, 2014/12/18