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Re: [Qemu-ppc] [RFC v1 05/13] target-ppc: add modulo word operations
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [RFC v1 05/13] target-ppc: add modulo word operations |
Date: |
Fri, 22 Jul 2016 14:51:37 +1000 |
User-agent: |
Mutt/1.6.2 (2016-07-01) |
On Mon, Jul 18, 2016 at 10:35:09PM +0530, Nikunj A Dadhania wrote:
> Adding following instructions:
>
> moduw: Modulo Unsigned Word
> modsw: Modulo Signed Word
>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
As rth has already mentioned this many branches probably means this
wants a helper.
> ---
> target-ppc/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index d44f7af..487dd94 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -1178,6 +1178,52 @@ GEN_DIVE(divde, divde, 0);
> GEN_DIVE(divdeo, divde, 1);
> #endif
>
> +static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1,
> + TCGv arg2, int sign)
> +{
> + TCGLabel *l1 = gen_new_label();
> + TCGLabel *l2 = gen_new_label();
> + TCGv_i32 t0 = tcg_temp_local_new_i32();
> + TCGv_i32 t1 = tcg_temp_local_new_i32();
> + TCGv_i32 t2 = tcg_temp_local_new_i32();
> +
> + tcg_gen_trunc_tl_i32(t0, arg1);
> + tcg_gen_trunc_tl_i32(t1, arg2);
> + tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
> + if (sign) {
> + TCGLabel *l3 = gen_new_label();
> + tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
> + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
> + gen_set_label(l3);
It's not really clear to be what the logic above is doing.
> + tcg_gen_rem_i32(t2, t0, t1);
> + } else {
> + tcg_gen_remu_i32(t2, t0, t1);
> + }
> + tcg_gen_br(l2);
> + gen_set_label(l1);
> + if (sign) {
> + tcg_gen_sari_i32(t2, t0, 31);
AFAICT this sets t2 to either 0 or -1 depending on the sign of t0,
which seems like an odd thing to do.
> + } else {
> + tcg_gen_movi_i32(t2, 0);
> + }
> + gen_set_label(l2);
> + tcg_gen_extu_i32_tl(ret, t2);
> + tcg_temp_free_i32(t0);
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(t2);
> +}
> +
> +#define GEN_INT_ARITH_MODW(name, opc3, sign) \
> +static void glue(gen_, name)(DisasContext *ctx) \
> +{ \
> + gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
> + cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
> + sign); \
> +}
> +
> +GEN_INT_ARITH_MODW(modsw, 0x18, 1);
> +GEN_INT_ARITH_MODW(moduw, 0x08, 0);
> +
> /* mulhw mulhw. */
> static void gen_mulhw(DisasContext *ctx)
> {
> @@ -10244,6 +10290,8 @@ GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE,
> PPC2_DIVE_ISA206),
> GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
> GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
> GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
> +GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300),
> +GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300),
>
> #if defined(TARGET_PPC64)
> #undef GEN_INT_ARITH_DIVD
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [RFC v1 00/13] POWER9 TCG enablements - part1, Nikunj A Dadhania, 2016/07/18
- [Qemu-ppc] [RFC v1 02/13] target-ppc: Introduce POWER ISA 3.0 flag, Nikunj A Dadhania, 2016/07/18
- [Qemu-ppc] [RFC v1 03/13] target-ppc: adding addpcis instruction, Nikunj A Dadhania, 2016/07/18
- [Qemu-ppc] [RFC v1 01/13] target-ppc: Introduce Power9 family, Nikunj A Dadhania, 2016/07/18
- [Qemu-ppc] [RFC v1 05/13] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/18
- Re: [Qemu-ppc] [RFC v1 05/13] target-ppc: add modulo word operations,
David Gibson <=
- Re: [Qemu-ppc] [RFC v1 05/13] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/22
- Re: [Qemu-ppc] [RFC v1 05/13] target-ppc: add modulo word operations, David Gibson, 2016/07/22
- Re: [Qemu-ppc] [RFC v1 05/13] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/22
- Re: [Qemu-ppc] [RFC v1 05/13] target-ppc: add modulo word operations, David Gibson, 2016/07/22
- Re: [Qemu-ppc] [RFC v1 05/13] target-ppc: add modulo word operations, Nikunj A Dadhania, 2016/07/22
[Qemu-ppc] [RFC v1 06/13] target-ppc: add modulo dword operations, Nikunj A Dadhania, 2016/07/18
[Qemu-ppc] [RFC v1 04/13] target-ppc: add cmprb instruction, Nikunj A Dadhania, 2016/07/18
[Qemu-ppc] [RFC v1 07/13] target-ppc: add cnttzd[.] instruction, Nikunj A Dadhania, 2016/07/18