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[Qemu-ppc] [RFC v2 07/13] target-ppc: add cnttzd[.] instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [RFC v2 07/13] target-ppc: add cnttzd[.] instruction |
Date: |
Sat, 23 Jul 2016 14:14:44 +0530 |
From: Sandipan Das <address@hidden>
Add ISA3.0 Count trailing zeros double word
Signed-off-by: Sandipan Das <address@hidden>
[ added ISA300 flag ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +++++
target-ppc/translate.c | 10 ++++++++++
3 files changed, 16 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 26a0930..8a3eb5d 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -48,6 +48,7 @@ DEF_HELPER_3(sraw, tl, env, tl, tl)
DEF_HELPER_FLAGS_2(modsd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(modud, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_1(cntlzd, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(cnttzd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntd, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(bpermd, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_3(srad, tl, env, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index e95572b..1d02e8a 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -181,6 +181,11 @@ target_ulong helper_cntlzd(target_ulong t)
{
return clz64(t);
}
+
+target_ulong helper_cnttzd(target_ulong t)
+{
+ return ctz64(t);
+}
#endif
#if defined(TARGET_PPC64)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 38a117c..1fc1922 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1760,6 +1760,15 @@ static void gen_cntlzd(DisasContext *ctx)
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
+
+/* cnttzd */
+static void gen_cnttzd(DisasContext *ctx)
+{
+ gen_helper_cnttzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
+ }
+}
#endif
/*** Integer rotate ***/
@@ -9997,6 +10006,7 @@ GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801,
PPC_NONE, PPC2_ISA205),
#if defined(TARGET_PPC64)
GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
+GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE,
PPC2_PERM_ISA206),
#endif
--
2.7.4
[Qemu-ppc] [RFC v2 06/13] target-ppc: add modulo dword operations, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 08/13] target-ppc: add cnttzw[.] instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 09/13] target-ppc: add cmpeqb instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 10/13] target-ppc: add setb instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 07/13] target-ppc: add cnttzd[.] instruction,
Nikunj A Dadhania <=
[Qemu-ppc] [RFC v2 11/13] target-ppc: add maddld instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 12/13] target-ppc: add maddhd and maddhdu instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 13/13] target-ppc: introduce opc4 for Expanded Opcode, Nikunj A Dadhania, 2016/07/23