[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-ppc] [PATCH 13/32] ppc: Don't update NIP in lswi/lswx/stswi/st
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [PATCH 13/32] ppc: Don't update NIP in lswi/lswx/stswi/stswx |
Date: |
Wed, 27 Jul 2016 12:04:43 +1000 |
User-agent: |
Mutt/1.6.2 (2016-07-01) |
On Wed, Jul 27, 2016 at 08:21:07AM +1000, Benjamin Herrenschmidt wrote:
> Instead, pass GETPC() result to the corresponding helpers. This
> requires a bit of fiddling to get the PC (hopefully) right in
> the case where we generate a program check, though the hacks there
> are temporary, a subsequent patch will clean this all up by always
> having the nip already set to the right instruction when taking
> the fault.
Where are cpu_ldub_data() and cpu_ldub_data_ra() defined? I assume
it's via macro somewhere, since I couldn't find it with a grep.
>
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> ---
> target-ppc/excp_helper.c | 8 ++++++++
> target-ppc/mem_helper.c | 26 ++++++++++++++++----------
> target-ppc/translate.c | 18 ++++++++----------
> 3 files changed, 32 insertions(+), 20 deletions(-)
>
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index 91fdf4b..563c7bc 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -285,6 +285,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip);
> msr |= 0x00080000;
> env->spr[SPR_BOOKE_ESR] = ESR_PIL;
> + /* Some invalids will have the PC in the right place already */
> + if (env->error_code & POWERPC_EXCP_INVAL_LSWX) {
> + goto store_next;
> + }
> break;
> case POWERPC_EXCP_PRIV:
> msr |= 0x00040000;
> @@ -306,6 +310,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
> excp_model, int excp)
> srr1 = SPR_HSRR1;
> new_msr |= (target_ulong)MSR_HVB;
> new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
> + /* Some invalids will have the PC in the right place already */
> + if (env->error_code == (POWERPC_EXCP_INVAL|POWERPC_EXCP_INVAL_LSWX))
> {
> + goto store_next;
> + }
> goto store_current;
> case POWERPC_EXCP_FPU: /* Floating-point unavailable exception
> */
> goto store_current;
> diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
> index e4ed377..de96c91 100644
> --- a/target-ppc/mem_helper.c
> +++ b/target-ppc/mem_helper.c
> @@ -77,23 +77,30 @@ void helper_stmw(CPUPPCState *env, target_ulong addr,
> uint32_t reg)
> }
> }
>
> -void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t
> reg)
> +static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
> + uint32_t reg, uintptr_t raddr)
> {
> int sh;
>
> for (; nb > 3; nb -= 4) {
> - env->gpr[reg] = cpu_ldl_data(env, addr);
> + env->gpr[reg] = cpu_ldl_data_ra(env, addr, raddr);
> reg = (reg + 1) % 32;
> addr = addr_add(env, addr, 4);
> }
> if (unlikely(nb > 0)) {
> env->gpr[reg] = 0;
> for (sh = 24; nb > 0; nb--, sh -= 8) {
> - env->gpr[reg] |= cpu_ldub_data(env, addr) << sh;
> + env->gpr[reg] |= cpu_ldub_data_ra(env, addr, raddr) << sh;
> addr = addr_add(env, addr, 1);
> }
> }
> }
> +
> +void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t
> reg)
> +{
> + do_lsw(env, addr, nb, reg, GETPC());
> +}
> +
> /* PPC32 specification says we must generate an exception if
> * rA is in the range of registers to be loaded.
> * In an other hand, IBM says this is valid, but rA won't be loaded.
> @@ -106,12 +113,11 @@ void helper_lswx(CPUPPCState *env, target_ulong addr,
> uint32_t reg,
> int num_used_regs = (xer_bc + 3) / 4;
> if (unlikely((ra != 0 && lsw_reg_in_range(reg, num_used_regs, ra)) ||
> lsw_reg_in_range(reg, num_used_regs, rb))) {
> - env->nip += 4; /* Compensate the "nip - 4" from gen_lswx() */
> - helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
> - POWERPC_EXCP_INVAL |
> - POWERPC_EXCP_INVAL_LSWX);
> + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
> + POWERPC_EXCP_INVAL |
> + POWERPC_EXCP_INVAL_LSWX, GETPC());
> } else {
> - helper_lsw(env, addr, xer_bc, reg);
> + do_lsw(env, addr, xer_bc, reg, GETPC());
> }
> }
> }
> @@ -122,13 +128,13 @@ void helper_stsw(CPUPPCState *env, target_ulong addr,
> uint32_t nb,
> int sh;
>
> for (; nb > 3; nb -= 4) {
> - cpu_stl_data(env, addr, env->gpr[reg]);
> + cpu_stl_data_ra(env, addr, env->gpr[reg], GETPC());
> reg = (reg + 1) % 32;
> addr = addr_add(env, addr, 4);
> }
> if (unlikely(nb > 0)) {
> for (sh = 24; nb > 0; nb--, sh -= 8) {
> - cpu_stb_data(env, addr, (env->gpr[reg] >> sh) & 0xFF);
> + cpu_stb_data_ra(env, addr, (env->gpr[reg] >> sh) & 0xFF,
> GETPC());
> addr = addr_add(env, addr, 1);
> }
> }
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index a05fed7..9d2e923 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -2701,12 +2701,16 @@ static void gen_lswi(DisasContext *ctx)
> nb = 32;
> nr = (nb + 3) / 4;
> if (unlikely(lsw_reg_in_range(start, nr, ra))) {
> + /* The handler expects the PC to point to *this* instruction,
> + * so setting ctx->exception here prevents it from being
> + * improperly updated again by gen_inval_exception
> + */
> + gen_update_nip(ctx, ctx->nip - 4);
> + ctx->exception = POWERPC_EXCP_HV_EMU;
> gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
> return;
> }
> gen_set_access_type(ctx, ACCESS_INT);
> - /* NIP cannot be restored if the memory exception comes from an helper */
> - gen_update_nip(ctx, ctx->nip - 4);
> t0 = tcg_temp_new();
> gen_addr_register(ctx, t0);
> t1 = tcg_const_i32(nb);
> @@ -2723,8 +2727,6 @@ static void gen_lswx(DisasContext *ctx)
> TCGv t0;
> TCGv_i32 t1, t2, t3;
> gen_set_access_type(ctx, ACCESS_INT);
> - /* NIP cannot be restored if the memory exception comes from an helper */
> - gen_update_nip(ctx, ctx->nip - 4);
> t0 = tcg_temp_new();
> gen_addr_reg_index(ctx, t0);
> t1 = tcg_const_i32(rD(ctx->opcode));
> @@ -2744,8 +2746,6 @@ static void gen_stswi(DisasContext *ctx)
> TCGv_i32 t1, t2;
> int nb = NB(ctx->opcode);
> gen_set_access_type(ctx, ACCESS_INT);
> - /* NIP cannot be restored if the memory exception comes from an helper */
> - gen_update_nip(ctx, ctx->nip - 4);
> t0 = tcg_temp_new();
> gen_addr_register(ctx, t0);
> if (nb == 0)
> @@ -2764,8 +2764,6 @@ static void gen_stswx(DisasContext *ctx)
> TCGv t0;
> TCGv_i32 t1, t2;
> gen_set_access_type(ctx, ACCESS_INT);
> - /* NIP cannot be restored if the memory exception comes from an helper */
> - gen_update_nip(ctx, ctx->nip - 4);
> t0 = tcg_temp_new();
> gen_addr_reg_index(ctx, t0);
> t1 = tcg_temp_new_i32();
> @@ -3846,7 +3844,7 @@ static void gen_dcbz(DisasContext *ctx)
> static void gen_dst(DisasContext *ctx)
> {
> if (rA(ctx->opcode) == 0) {
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
> + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> } else {
> /* interpreted as no-op */
> }
> @@ -3856,7 +3854,7 @@ static void gen_dst(DisasContext *ctx)
> static void gen_dstst(DisasContext *ctx)
> {
> if (rA(ctx->opcode) == 0) {
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
> + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> } else {
> /* interpreted as no-op */
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
signature.asc
Description: PGP signature
- [Qemu-ppc] [PATCH 01/32] ppc: Fix fault PC reporting for lve*/stve* VMX instructions, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 02/32] ppc: Provide basic raise_exception_* functions, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 05/32] ppc: Move DFP ops out of translate.c, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 09/32] ppc: Make float_invalid_op_excp() pass the return address, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 15/32] ppc: Make tlb_fill() use new exception helper, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 13/32] ppc: Don't update NIP in lswi/lswx/stswi/stswx, Benjamin Herrenschmidt, 2016/07/26
- Re: [Qemu-ppc] [PATCH 13/32] ppc: Don't update NIP in lswi/lswx/stswi/stswx,
David Gibson <=
- [Qemu-ppc] [PATCH 10/32] ppc: Make float_check_status() pass the return address, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 12/32] ppc: FP exceptions are always precise, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 11/32] ppc: Don't update the NIP in floating point generated code, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 08/32] ppc: Rename fload_invalid_op_excp to float_invalid_op_excp, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 03/32] ppc: Move classic fp ops out of translate.c, Benjamin Herrenschmidt, 2016/07/26