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Re: [Qemu-ppc] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mas
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mask define |
Date: |
Mon, 13 Feb 2017 12:59:53 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Fri, Feb 10, 2017 at 04:25:52PM +1100, Suraj Jitindar Singh wrote:
> The DPFD field in the LPCR is 3 bits wide. This has always been defined
> as 0x3 << shift which indicates a 2 bit field, which is incorrect.
> Correct this.
>
> Signed-off-by: Suraj Jitindar Singh <address@hidden>
Since this is a correct fix all on its own, I've applied it to
ppc-for-2.9.
> ---
> target/ppc/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index bc2a2ce..bb96dd5 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -381,7 +381,7 @@ struct ppc_slb_t {
> #define LPCR_ISL (1ull << (63 - 2))
> #define LPCR_KBV (1ull << (63 - 3))
> #define LPCR_DPFD_SHIFT (63 - 11)
> -#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT)
> +#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
> #define LPCR_VRMASD_SHIFT (63 - 16)
> #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
> #define LPCR_RMLS_SHIFT (63 - 37)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-ppc] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg, Suraj Jitindar Singh, 2017/02/10
- [Qemu-ppc] [QEMU-PPC] [PATCH V2 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition, Suraj Jitindar Singh, 2017/02/10
- [Qemu-ppc] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mask define, Suraj Jitindar Singh, 2017/02/10
- Re: [Qemu-ppc] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mask define,
David Gibson <=
- [Qemu-ppc] [QEMU-PPC] [PATCH V2 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9, Suraj Jitindar Singh, 2017/02/10
- [Qemu-ppc] [QEMU-PPC] [PATCH V2 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv, Suraj Jitindar Singh, 2017/02/10
- [Qemu-ppc] [QEMU-PPC] [PATCH V2 05/10] target/ppc: Add patb_entry to sPAPRMachineState, Suraj Jitindar Singh, 2017/02/10
- [Qemu-ppc] [QEMU-PPC] [PATCH V2 06/10] target/ppc: Don't use SDR1 when running under a POWER9 cpu model, Suraj Jitindar Singh, 2017/02/10
- [Qemu-ppc] [QEMU-PPC] [PATCH V2 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/02/10
- [Qemu-ppc] [QEMU-PPC] [PATCH V2 08/10] target/ppc/POWER9: Add POWER9 pa-features definition, Suraj Jitindar Singh, 2017/02/10