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[Qemu-ppc] [PATCH v2 08/19] spapr: notify the CPU when the XIVE interrup
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH v2 08/19] spapr: notify the CPU when the XIVE interrupt priority is more privileged |
Date: |
Sat, 9 Dec 2017 09:43:27 +0100 |
Once an event has been routed, the XIVE virtualization presenter
engine raises the bit corresponding to the priority of the pending
interrupt in the register IBP (Interrupt Pending Buffer). The Pending
Interrupt Priority Register (PIPR) is also updated using the IPB. It
contains the priority of the most favored pending notification.
The PIPR is then compared to the the Current Processor Priority
Register (CPPR). If it is more favored (numerically less than), the
CPU interrupt line is raised and the EO bit of the Notification Source
Register (NSR) is updated to notify the presence of an exception for
the O/S. The check needs to be done whenever the PIPR or the CPPR are
changed.
The O/S acknowledges the interrupt with a special load in the Thread
Interrupt Management Area. If the EO bit of the NSR is set, the CPPR
takes the value of PIPR. The bit number in the IBP corresponding to
the priority of the pending interrupt is reseted and so is the EO bit
of the NSR.
Signed-off-by: Cédric Le Goater <address@hidden>
---
Changes since v1:
- set initial TM_PIPR to 0xFF
hw/intc/spapr_xive.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 88 insertions(+), 1 deletion(-)
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index 629563d01998..a8acfee740d9 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -35,9 +35,68 @@ struct sPAPRXiveNVT {
XiveEQ eqt[XIVE_PRIORITY_MAX + 1];
};
+/* Convert a priority number to an Interrupt Pending Buffer (IPB)
+ * register, which indicates a pending interrupt at the priority
+ * corresponding to the bit number
+ */
+static uint8_t priority_to_ipb(uint8_t priority)
+{
+ return priority > XIVE_PRIORITY_MAX ?
+ 0 : 1 << (XIVE_PRIORITY_MAX - priority);
+}
+
+/* Convert an Interrupt Pending Buffer (IPB) register to a Pending
+ * Interrupt Priority Register (PIPR), which contains the priority of
+ * the most favored pending notification.
+ */
+static uint8_t ipb_to_pipr(uint8_t ibp)
+{
+ return ibp ? clz32((uint32_t)ibp << 24) : 0xff;
+}
+
+/*
+ * TODO:
+ *
+ * Ben says: "
+ *
+ * PIPR is clamped to CPPR. So the value in the PIPR is:
+ *
+ * v = leftmost_bit_of(ipb) (or 0xff);
+ * pipr = v < cppr ? v : cppr;
+ *
+ * which means it's never actually 0xff ... surprise !".
+ *
+ * But, the CPPR is set to 0xFF by the OS and so the PIPR will always
+ * be more favored ... I am confused ...
+ */
static uint64_t spapr_xive_nvt_accept(sPAPRXiveNVT *nvt)
{
- return 0;
+ uint8_t nsr = nvt->ring_os[TM_NSR];
+
+ qemu_irq_lower(nvt->output);
+
+ if (nvt->ring_os[TM_NSR] & TM_QW1_NSR_EO) {
+ uint8_t cppr = nvt->ring_os[TM_PIPR];
+
+ nvt->ring_os[TM_CPPR] = cppr;
+
+ /* Reset the pending buffer bit */
+ nvt->ring_os[TM_IPB] &= ~priority_to_ipb(cppr);
+ nvt->ring_os[TM_PIPR] = ipb_to_pipr(nvt->ring_os[TM_IPB]);
+
+ /* Drop Exception bit for OS */
+ nvt->ring_os[TM_NSR] &= ~TM_QW1_NSR_EO;
+ }
+
+ return (nsr << 8) | nvt->ring_os[TM_CPPR];
+}
+
+static void spapr_xive_nvt_notify(sPAPRXiveNVT *nvt)
+{
+ if (nvt->ring_os[TM_PIPR] < nvt->ring_os[TM_CPPR]) {
+ nvt->ring_os[TM_NSR] |= TM_QW1_NSR_EO;
+ qemu_irq_raise(nvt->output);
+ }
}
static void spapr_xive_nvt_set_cppr(sPAPRXiveNVT *nvt, uint8_t cppr)
@@ -47,6 +106,10 @@ static void spapr_xive_nvt_set_cppr(sPAPRXiveNVT *nvt,
uint8_t cppr)
}
nvt->ring_os[TM_CPPR] = cppr;
+
+ /* CPPR has changed, check if we need to redistribute a pending
+ * exception */
+ spapr_xive_nvt_notify(nvt);
}
/*
@@ -239,6 +302,8 @@ static void spapr_xive_irq(sPAPRXive *xive, int lisn)
XiveEQ *eq;
uint32_t eq_idx;
uint8_t priority;
+ uint32_t server;
+ sPAPRXiveNVT *nvt;
ive = spapr_xive_get_ive(xive, lisn);
if (!ive || !(ive->w & IVE_VALID)) {
@@ -267,6 +332,13 @@ static void spapr_xive_irq(sPAPRXive *xive, int lisn)
qemu_log_mask(LOG_UNIMP, "XIVE: !UCOND_NOTIFY not implemented\n");
}
+ server = GETFIELD(EQ_W6_NVT_INDEX, eq->w6);
+ nvt = spapr_xive_nvt_get(xive, server);
+ if (!nvt) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVT for server %d\n", server);
+ return;
+ }
+
if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {
priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);
@@ -274,9 +346,18 @@ static void spapr_xive_irq(sPAPRXive *xive, int lisn)
if (priority == 0xff) {
g_assert_not_reached();
}
+
+ /* Update the IPB (Interrupt Pending Buffer) with the priority
+ * of the new notification and inform the NVT, which will
+ * decide to raise the exception, or not, depending the CPPR.
+ */
+ nvt->ring_os[TM_IPB] |= priority_to_ipb(priority);
+ nvt->ring_os[TM_PIPR] = ipb_to_pipr(nvt->ring_os[TM_IPB]);
} else {
qemu_log_mask(LOG_UNIMP, "XIVE: w7 format1 not implemented\n");
}
+
+ spapr_xive_nvt_notify(nvt);
}
/*
@@ -717,6 +798,12 @@ static void spapr_xive_nvt_reset(void *dev)
memset(nvt->regs, 0, sizeof(nvt->regs));
+ /*
+ * Initialize PIPR to 0xFF to avoid phantom interrupts when the
+ * CPPR is first set.
+ */
+ nvt->ring_os[TM_PIPR] = ipb_to_pipr(nvt->ring_os[TM_IPB]);
+
memset(nvt->eqt, 0, sizeof(nvt->eqt));
}
--
2.13.6
- Re: [Qemu-ppc] [PATCH v2 03/19] spapr: introduce the XIVE interrupt sources, (continued)
Re: [Qemu-ppc] [PATCH v2 03/19] spapr: introduce the XIVE interrupt sources, David Gibson, 2017/12/20
[Qemu-ppc] [PATCH v2 04/19] spapr: add support for the LSI interrupt sources, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 05/19] spapr: introduce a XIVE interrupt presenter model, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 06/19] spapr: introduce the XIVE Event Queues, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 07/19] spapr: push the XIVE EQ data in OS event queue, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 08/19] spapr: notify the CPU when the XIVE interrupt priority is more privileged,
Cédric Le Goater <=
[Qemu-ppc] [PATCH v2 09/19] spapr: add support for the SET_OS_PENDING command (XIVE), Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 10/19] spapr: introduce a 'xive_exploitation' boolean to enable XIVE, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 11/19] spapr: add a sPAPRXive object to the machine, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 12/19] spapr: add hcalls support for the XIVE exploitation interrupt mode, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 13/19] spapr: add device tree support for the XIVE interrupt mode, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 14/19] spapr: introduce a helper to map the XIVE memory regions, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 15/19] spapr: add XIVE support to spapr_qirq(), Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 16/19] spapr: introduce a spapr_icp_create() helper, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 17/19] spapr: toggle the ICP depending on the selected interrupt mode, Cédric Le Goater, 2017/12/09
[Qemu-ppc] [PATCH v2 18/19] spapr: add support to dump XIVE information, Cédric Le Goater, 2017/12/09