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[Qemu-ppc] [PULL 56/60] ppc/pnv: add a "ibm, opal/power-mgt" device tree
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 56/60] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9 |
Date: |
Sun, 10 Mar 2019 19:26:59 +1100 |
From: Cédric Le Goater <address@hidden>
Activate only stop0 and stop1 levels. We should not need more levels
when under QEMU.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/pnv.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index e68d419203..8be4d4cbf7 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -438,6 +438,16 @@ static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
&args);
}
+static void pnv_dt_power_mgt(void *fdt)
+{
+ int off;
+
+ off = fdt_add_subnode(fdt, 0, "ibm,opal");
+ off = fdt_add_subnode(fdt, off, "power-mgt");
+
+ _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
+}
+
static void *pnv_dt_create(MachineState *machine)
{
const char plat_compat[] = "qemu,powernv\0ibm,powernv";
@@ -493,6 +503,11 @@ static void *pnv_dt_create(MachineState *machine)
pnv_dt_bmc_sensors(pnv->bmc, fdt);
}
+ /* Create an extra node for power management on Power9 */
+ if (pnv_is_power9(pnv)) {
+ pnv_dt_power_mgt(fdt);
+ }
+
return fdt;
}
--
2.20.1
- [Qemu-ppc] [PULL 40/60] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}(), (continued)
- [Qemu-ppc] [PULL 40/60] target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l, h}() and set_cpu_vsr{l, h}(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 37/60] target/ppc: introduce avr_full_offset() function, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 26/60] ppc/pnv: add a XIVE interrupt controller model for POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 35/60] target/ppc: introduce single vsrl_offset() function, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 34/60] target/ppc: introduce single fpr_offset() function, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 39/60] target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian order, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 43/60] ppc/pnv: add a PSI bridge class model, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 33/60] spapr_iommu: Do not replay mappings from just created DMA window, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 42/60] mac_newworld: use node name instead of alias name for hd device in FWPathProvider, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 38/60] target/ppc: improve avr64_offset() and use it to simplify get_avr64()/set_avr64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 56/60] ppc/pnv: add a "ibm, opal/power-mgt" device tree node on POWER9,
David Gibson <=
- [Qemu-ppc] [PULL 36/60] target/ppc: move Vsr* macros from internal.h to cpu.h, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 58/60] target/ppc: Optimize xviexpdp() using deposit_i64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 50/60] ppc/pnv: add a OCC model class, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 45/60] ppc/pnv: lpc: fix OPB address ranges, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 49/60] ppc/pnv: add SerIRQ routing registers, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 54/60] ppc/pnv: activate XSCOM tests for POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 51/60] ppc/pnv: add a OCC model for POWER9, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 47/60] ppc/pnv: add a 'dt_isa_nodename' to the chip, David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 59/60] target/ppc: Optimize x[sv]xsigdp using deposit_i64(), David Gibson, 2019/03/10
- [Qemu-ppc] [PULL 44/60] ppc/pnv: add a PSI bridge model for POWER9, David Gibson, 2019/03/10