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[PULL 094/101] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PE
From: |
Cédric Le Goater |
Subject: |
[PULL 094/101] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices |
Date: |
Thu, 16 Dec 2021 21:26:07 +0100 |
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attribute represents better the logic units of the
POWER9 chip. Use that instead of num_phbs which fits POWER8 chips.
This will ease adding support for user created devices.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211213132830.108372-8-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 2 ++
hw/ppc/pnv.c | 19 ++++++++-----------
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index aa08d79d24de..c781525277db 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -53,6 +53,7 @@ struct PnvChip {
PnvCore **cores;
uint32_t num_phbs;
+ uint32_t num_pecs;
MemoryRegion xscom_mmio;
MemoryRegion xscom;
@@ -136,6 +137,7 @@ struct PnvChipClass {
uint64_t chip_cfam_id;
uint64_t cores_mask;
uint32_t num_phbs;
+ uint32_t num_pecs;
DeviceRealize parent_realize;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index e75fc999ee11..2fc2b0dff7a3 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -667,7 +667,7 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip,
Monitor *mon)
pnv_xive_pic_print_info(&chip9->xive, mon);
pnv_psi_pic_print_info(&chip9->psi, mon);
- for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
+ for (i = 0; i < chip->num_pecs; i++) {
PnvPhb4PecState *pec = &chip9->pecs[i];
for (j = 0; j < pec->num_stacks; j++) {
pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon);
@@ -1344,15 +1344,13 @@ static void pnv_chip_power9_instance_init(Object *obj)
object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
- for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
+ /* Number of PECs is the chip default */
+ chip->num_pecs = pcc->num_pecs;
+
+ for (i = 0; i < chip->num_pecs; i++) {
object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
TYPE_PNV_PHB4_PEC);
}
-
- /*
- * Number of PHBs is the chip default
- */
- chip->num_phbs = pcc->num_phbs;
}
static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
@@ -1388,7 +1386,7 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip,
Error **errp)
int i, j;
int phb_id = 0;
- for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) {
+ for (i = 0; i < chip->num_pecs; i++) {
PnvPhb4PecState *pec = &chip9->pecs[i];
PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
uint32_t pec_nest_base;
@@ -1416,8 +1414,7 @@ static void pnv_chip_power9_phb_realize(PnvChip *chip,
Error **errp)
pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
- for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs;
- j++, phb_id++) {
+ for (j = 0; j < pec->num_stacks; j++, phb_id++) {
PnvPhb4PecStack *stack = &pec->stacks[j];
Object *obj = OBJECT(&stack->phb);
@@ -1573,7 +1570,7 @@ static void pnv_chip_power9_class_init(ObjectClass
*klass, void *data)
k->xscom_core_base = pnv_chip_power9_xscom_core_base;
k->xscom_pcba = pnv_chip_power9_xscom_pcba;
dc->desc = "PowerNV Chip POWER9";
- k->num_phbs = 6;
+ k->num_pecs = PNV9_CHIP_MAX_PEC;
device_class_set_parent_realize(dc, pnv_chip_power9_realize,
&k->parent_realize);
--
2.31.1
- [PULL 088/101] PPC64/TCG: Implement 'rfebb' instruction, (continued)
- [PULL 088/101] PPC64/TCG: Implement 'rfebb' instruction, Cédric Le Goater, 2021/12/16
- [PULL 101/101] ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices, Cédric Le Goater, 2021/12/16
- [PULL 083/101] target/ppc: PMU: update counters on PMCs r/w, Cédric Le Goater, 2021/12/16
- [PULL 099/101] ppc/pnv: Remove "system-memory" property from PHB4 PEC, Cédric Le Goater, 2021/12/16
- [PULL 082/101] target/ppc: PMU basic cycle count for pseries TCG, Cédric Le Goater, 2021/12/16
- [PULL 085/101] target/ppc: enable PMU counter overflow with cycle events, Cédric Le Goater, 2021/12/16
- [PULL 086/101] target/ppc: enable PMU instruction count, Cédric Le Goater, 2021/12/16
- [PULL 097/101] ppc/pnv: Introduce a num_stack class attribute, Cédric Le Goater, 2021/12/16
- [PULL 084/101] target/ppc: PMU: update counters on MMCR1 write, Cédric Le Goater, 2021/12/16
- [PULL 079/101] target/ppc: Fix e6500 boot, Cédric Le Goater, 2021/12/16
- [PULL 094/101] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices,
Cédric Le Goater <=
- [PULL 098/101] ppc/pnv: Compute the PHB index from the PHB4 PEC model, Cédric Le Goater, 2021/12/16
- [PULL 100/101] ppc/pnv: Move realize of PEC stacks under the PEC model, Cédric Le Goater, 2021/12/16
- [PULL 089/101] ppc/pnv: Introduce a "chip" property under PHB3, Cédric Le Goater, 2021/12/16
- Re: [PULL v2 000/101] ppc queue, Richard Henderson, 2021/12/17