[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 35/42] target/ppc: 7xx: Set SRRs directly in exception code
From: |
Cédric Le Goater |
Subject: |
[PULL 35/42] target/ppc: 7xx: Set SRRs directly in exception code |
Date: |
Thu, 10 Feb 2022 14:00:01 +0100 |
From: Fabiano Rosas <farosas@linux.ibm.com>
The 7xx CPUs don't have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index dd373a4d5b39..0eb6b7af5586 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -746,7 +746,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
target_ulong msr, new_msr, vector;
- int srr0, srr1;
if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
@@ -765,10 +764,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
*/
new_msr = env->msr & ((target_ulong)1 << MSR_ME);
- /* target registers */
- srr0 = SPR_SRR0;
- srr1 = SPR_SRR1;
-
/*
* Hypervisor emulation assistance interrupt only exists on server
* arch 2.05 server or later.
@@ -929,10 +924,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
"no HV support\n", excp);
}
- if (srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
- }
}
/*
@@ -944,10 +935,10 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
}
/* Save PC */
- env->spr[srr0] = env->nip;
+ env->spr[SPR_SRR0] = env->nip;
/* Save MSR */
- env->spr[srr1] = msr;
+ env->spr[SPR_SRR1] = msr;
powerpc_set_excp_state(cpu, vector, new_msr);
}
--
2.34.1
- [PULL 05/42] target/ppc: booke: Machine Check cleanups, (continued)
- [PULL 05/42] target/ppc: booke: Machine Check cleanups, Cédric Le Goater, 2022/02/10
- [PULL 17/42] target/ppc: Simplify powerpc_excp_6xx, Cédric Le Goater, 2022/02/10
- [PULL 26/42] target/ppc: Merge 7x5 and 7x0 exception model IDs, Cédric Le Goater, 2022/02/10
- [PULL 13/42] target/ppc: Fix radix logging, Cédric Le Goater, 2022/02/10
- [PULL 38/42] target/ppc: Assert if MSR bits differ from msr_mask during exceptions, Cédric Le Goater, 2022/02/10
- [PULL 16/42] target/ppc: Introduce powerpc_excp_6xx, Cédric Le Goater, 2022/02/10
- [PULL 24/42] target/ppc: 6xx: Software TLB exceptions cleanup, Cédric Le Goater, 2022/02/10
- [PULL 28/42] target/ppc: Simplify powerpc_excp_7xx, Cédric Le Goater, 2022/02/10
- [PULL 22/42] target/ppc: 6xx: System Call exception cleanup, Cédric Le Goater, 2022/02/10
- [PULL 33/42] target/ppc: 7xx: System Reset cleanup, Cédric Le Goater, 2022/02/10
- [PULL 35/42] target/ppc: 7xx: Set SRRs directly in exception code,
Cédric Le Goater <=
- [PULL 27/42] target/ppc: Introduce powerpc_excp_7xx, Cédric Le Goater, 2022/02/10
- [PULL 41/42] docs: rstfy confidential guest documentation, Cédric Le Goater, 2022/02/10
- [PULL 03/42] target/ppc: Simplify powerpc_excp_booke, Cédric Le Goater, 2022/02/10
- [PULL 29/42] target/ppc: 7xx: Machine Check exception cleanup, Cédric Le Goater, 2022/02/10
- [PULL 40/42] target/ppc: Change VSX instructions behavior to fill with zeros, Cédric Le Goater, 2022/02/10
- [PULL 25/42] target/ppc: 6xx: Set SRRs directly in exception code, Cédric Le Goater, 2022/02/10
- Re: [PULL 00/42] ppc queue, Peter Maydell, 2022/02/14