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[PATCH v4 06/47] target/ppc: Implement vmsumudm instruction
From: |
matheus . ferst |
Subject: |
[PATCH v4 06/47] target/ppc: Implement vmsumudm instruction |
Date: |
Tue, 22 Feb 2022 11:36:04 -0300 |
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Based on [1] by Lijun Pan <ljp@linux.ibm.com>, which was never merged
into master.
[1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 34 +++++++++++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e85a75db2f..732a2bb79e 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -471,6 +471,7 @@ VMULLD 000100 ..... ..... ..... 00111001001 @VX
## Vector Multiply-Sum Instructions
VMSUMCUD 000100 ..... ..... ..... ..... 010111 @VA
+VMSUMUDM 000100 ..... ..... ..... ..... 100011 @VA
# VSX Load/Store Instructions
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index e029873ae0..afe895ab7f 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2081,6 +2081,40 @@ static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
return true;
}
+static bool trans_VMSUMUDM(DisasContext *ctx, arg_VA *a)
+{
+ TCGv_i64 rl, rh, src1, src2;
+ int dw;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VECTOR(ctx);
+
+ rh = tcg_temp_new_i64();
+ rl = tcg_temp_new_i64();
+ src1 = tcg_temp_new_i64();
+ src2 = tcg_temp_new_i64();
+
+ get_avr64(rl, a->rc, false);
+ get_avr64(rh, a->rc, true);
+
+ for (dw = 0; dw < 2; dw++) {
+ get_avr64(src1, a->vra, dw);
+ get_avr64(src2, a->vrb, dw);
+ tcg_gen_mulu2_i64(src1, src2, src1, src2);
+ tcg_gen_add2_i64(rl, rh, rl, rh, src1, src2);
+ }
+
+ set_avr64(a->vrt, rl, false);
+ set_avr64(a->vrt, rh, true);
+
+ tcg_temp_free_i64(rl);
+ tcg_temp_free_i64(rh);
+ tcg_temp_free_i64(src1);
+ tcg_temp_free_i64(src2);
+
+ return true;
+}
+
static bool trans_VMSUMCUD(DisasContext *ctx, arg_VA *a)
{
TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
--
2.25.1
- [PATCH v4 02/47] target/ppc: moved vector even and odd multiplication to decodetree, (continued)
- [PATCH v4 02/47] target/ppc: moved vector even and odd multiplication to decodetree, matheus . ferst, 2022/02/22
- [PATCH v4 03/47] target/ppc: Moved vector multiply high and low to decodetree, matheus . ferst, 2022/02/22
- [PATCH v4 05/47] target/ppc: Implement vmsumcud instruction, matheus . ferst, 2022/02/22
- [PATCH v4 04/47] target/ppc: vmulh* instructions without helpers, matheus . ferst, 2022/02/22
- [PATCH v4 07/47] target/ppc: Move vexts[bhw]2[wd] to decodetree, matheus . ferst, 2022/02/22
- [PATCH v4 06/47] target/ppc: Implement vmsumudm instruction,
matheus . ferst <=
- [PATCH v4 09/47] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree, matheus . ferst, 2022/02/22
- [PATCH v4 10/47] target/ppc: Move Vector Compare Not Equal or Zero to decodetree, matheus . ferst, 2022/02/22
- [PATCH v4 08/47] target/ppc: Implement vextsd2q, matheus . ferst, 2022/02/22
- [PATCH v4 12/47] target/ppc: Implement Vector Compare Greater Than Quadword, matheus . ferst, 2022/02/22
- [PATCH v4 11/47] target/ppc: Implement Vector Compare Equal Quadword, matheus . ferst, 2022/02/22
- [PATCH v4 13/47] target/ppc: Implement Vector Compare Quadword, matheus . ferst, 2022/02/22