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[PATCH v4 22/47] target/ppc: implement vsraq
From: |
matheus . ferst |
Subject: |
[PATCH v4 22/47] target/ppc: implement vsraq |
Date: |
Tue, 22 Feb 2022 11:36:20 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v4:
- New in v4.
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 17 +++++++++++++----
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 96ee730242..7a9fc1dffa 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -485,6 +485,7 @@ VSRAB 000100 ..... ..... ..... 01100000100 @VX
VSRAH 000100 ..... ..... ..... 01101000100 @VX
VSRAW 000100 ..... ..... ..... 01110000100 @VX
VSRAD 000100 ..... ..... ..... 01111000100 @VX
+VSRAQ 000100 ..... ..... ..... 01100000101 @VX
## Vector Integer Arithmetic Instructions
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index ec2b47b4aa..2eee187499 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -834,7 +834,8 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16,
tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
-static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
+static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
+ bool alg)
{
TCGv_i64 hi, lo, tmp, n, sf = tcg_constant_i64(64);
@@ -853,6 +854,9 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX
*a, bool right)
if (right) {
tcg_gen_movcond_i64(TCG_COND_GE, lo, n, sf, hi, lo);
+ if (alg) {
+ tcg_gen_sari_i64(tmp, lo, 63);
+ }
tcg_gen_movcond_i64(TCG_COND_GE, hi, n, sf, tmp, hi);
} else {
tcg_gen_movcond_i64(TCG_COND_GE, hi, n, sf, lo, hi);
@@ -861,7 +865,11 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX
*a, bool right)
tcg_gen_andi_i64(n, n, ~64ULL);
if (right) {
- tcg_gen_shr_i64(tmp, hi, n);
+ if (alg) {
+ tcg_gen_sar_i64(tmp, hi, n);
+ } else {
+ tcg_gen_shr_i64(tmp, hi, n);
+ }
} else {
tcg_gen_shl_i64(tmp, lo, n);
}
@@ -891,8 +899,9 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX
*a, bool right)
return true;
}
-TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false);
-TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true);
+TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false, false);
+TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true, false);
+TRANS_FLAGS2(ISA310, VSRAQ, do_vector_shift_quad, true, true);
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
--
2.25.1
- Re: [PATCH v4 15/47] target/ppc: implement vclrlb, (continued)
- [PATCH v4 17/47] target/ppc: implement vcntmb[bhwd], matheus . ferst, 2022/02/22
- [PATCH v4 22/47] target/ppc: implement vsraq,
matheus . ferst <=
- [PATCH v4 21/47] target/ppc: implement vsrq, matheus . ferst, 2022/02/22
- [PATCH v4 19/47] target/ppc: move vs[lr][a][bhwd] to decodetree, matheus . ferst, 2022/02/22
- [PATCH v4 23/47] target/ppc: move vrl[bhwd] to decodetree, matheus . ferst, 2022/02/22
- [PATCH v4 24/47] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree, matheus . ferst, 2022/02/22