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[PATCH v5 44/49] target/ppc: Refactor VSX_MAX_MINC helper
From: |
matheus . ferst |
Subject: |
[PATCH v5 44/49] target/ppc: Refactor VSX_MAX_MINC helper |
Date: |
Fri, 25 Feb 2022 18:09:31 -0300 |
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for
xs{max,min}cqp implementation.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
changes for v5:
- use float_flag_invalid_snan as suggested by Richard Henderson
---
target/ppc/fpu_helper.c | 41 +++++++++++++++++------------------------
1 file changed, 17 insertions(+), 24 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 4bfa1c4283..0aaf529ac8 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2533,40 +2533,33 @@ VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
-#define VSX_MAX_MINC(name, max) \
+#define VSX_MAX_MINC(name, max, tp, fld) \
void helper_##name(CPUPPCState *env, \
ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
- bool vxsnan_flag = false, vex_flag = false; \
+ bool first; \
\
- if (unlikely(float64_is_any_nan(xa->VsrD(0)) || \
- float64_is_any_nan(xb->VsrD(0)))) { \
- if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
- float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
- vxsnan_flag = true; \
- } \
- t.VsrD(0) = xb->VsrD(0); \
- } else if ((max && \
- !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
- (!max && \
- float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
- t.VsrD(0) = xa->VsrD(0); \
+ if (max) { \
+ first = tp##_le_quiet(xb->fld, xa->fld, &env->fp_status); \
} else { \
- t.VsrD(0) = xb->VsrD(0); \
+ first = tp##_lt_quiet(xa->fld, xb->fld, &env->fp_status); \
} \
\
- vex_flag = fpscr_ve & vxsnan_flag; \
- if (vxsnan_flag) { \
- float_invalid_op_vxsnan(env, GETPC()); \
+ if (first) { \
+ t.fld = xa->fld; \
+ } else { \
+ t.fld = xb->fld; \
+ if (env->fp_status.float_exception_flags & float_flag_invalid_snan) { \
+ float_invalid_op_vxsnan(env, GETPC()); \
+ } \
} \
- if (!vex_flag) { \
- *xt = t; \
- } \
-} \
+ \
+ *xt = t; \
+}
-VSX_MAX_MINC(XSMAXCDP, 1);
-VSX_MAX_MINC(XSMINCDP, 0);
+VSX_MAX_MINC(XSMAXCDP, true, float64, VsrD(0));
+VSX_MAX_MINC(XSMINCDP, false, float64, VsrD(0));
#define VSX_MAX_MINJ(name, max) \
void helper_##name(CPUPPCState *env, \
--
2.25.1
- [PATCH v5 36/49] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree, (continued)
- [PATCH v5 36/49] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree, matheus . ferst, 2022/02/25
- [PATCH v5 37/49] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o], matheus . ferst, 2022/02/25
- [PATCH v5 38/49] target/ppc: Implement xvtlsbb instruction, matheus . ferst, 2022/02/25
- [PATCH v5 39/49] target/ppc: Remove xscmpnedp instruction, matheus . ferst, 2022/02/25
- [PATCH v5 40/49] target/ppc: Refactor VSX_SCALAR_CMP_DP, matheus . ferst, 2022/02/25
- [PATCH v5 41/49] target/ppc: Implement xscmp{eq,ge,gt}qp, matheus . ferst, 2022/02/25
- [PATCH v5 42/49] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree, matheus . ferst, 2022/02/25
- [PATCH v5 43/49] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3, matheus . ferst, 2022/02/25
- [PATCH v5 44/49] target/ppc: Refactor VSX_MAX_MINC helper,
matheus . ferst <=
- [PATCH v5 45/49] target/ppc: Implement xs{max,min}cqp, matheus . ferst, 2022/02/25
- [PATCH v5 46/49] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions, matheus . ferst, 2022/02/25
- [PATCH v5 47/49] target/ppc: implement plxsd/pstxsd, matheus . ferst, 2022/02/25
- [PATCH v5 48/49] target/ppc: implement plxssp/pstxssp, matheus . ferst, 2022/02/25
- [PATCH v5 49/49] target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x, matheus . ferst, 2022/02/25