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[PATCH 2/5] ppc/pnv: Remove PnvLpcController::psi link
From: |
Cédric Le Goater |
Subject: |
[PATCH 2/5] ppc/pnv: Remove PnvLpcController::psi link |
Date: |
Wed, 23 Mar 2022 08:28:43 +0100 |
Create an anonymous output GPIO line to connect the LPC device with
the PSIHB device and raise the appropriate PSI IRQ line depending on
the processor model.
A temporary __pnv_psi_irq_set() routine is introduced to handle the
transition. It will be removed when all devices raising PSI interrupts
are converted to use GPIOs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv_lpc.h | 8 ++------
hw/ppc/pnv.c | 18 ++++++++++++------
hw/ppc/pnv_lpc.c | 19 ++++---------------
hw/ppc/pnv_psi.c | 10 ++++++++++
4 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index e893e763dd5f..8a8d1a3d4209 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV LPC controller
*
- * Copyright (c) 2016, IBM Corporation.
+ * Copyright (c) 2016-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -20,7 +20,6 @@
#ifndef PPC_PNV_LPC_H
#define PPC_PNV_LPC_H
-#include "hw/ppc/pnv_psi.h"
#include "qom/object.h"
#define TYPE_PNV_LPC "pnv-lpc"
@@ -84,15 +83,12 @@ struct PnvLpcController {
MemoryRegion xscom_regs;
/* PSI to generate interrupts */
- PnvPsi *psi;
+ qemu_irq psi_irq;
};
-
struct PnvLpcClass {
DeviceClass parent_class;
- int psi_irq;
-
DeviceRealize parent_realize;
};
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 00f57c9678e6..8082462bdfb1 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -615,24 +615,36 @@ static void pnv_reset(MachineState *machine)
static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
+
+ qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
return pnv_lpc_isa_create(&chip8->lpc, true, errp);
}
static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
+
+ qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
return pnv_lpc_isa_create(&chip8->lpc, false, errp);
}
static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
+
+ qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
return pnv_lpc_isa_create(&chip9->lpc, false, errp);
}
static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
{
Pnv10Chip *chip10 = PNV10_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
+
+ qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
return pnv_lpc_isa_create(&chip10->lpc, false, errp);
}
@@ -1223,8 +1235,6 @@ static void pnv_chip_power8_realize(DeviceState *dev,
Error **errp)
&PNV_PSI(psi8)->xscom_regs);
/* Create LPC controller */
- object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi),
- &error_abort);
qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
@@ -1508,8 +1518,6 @@ static void pnv_chip_power9_realize(DeviceState *dev,
Error **errp)
&PNV_PSI(psi9)->xscom_regs);
/* LPC */
- object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi),
- &error_abort);
if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
return;
}
@@ -1713,8 +1721,6 @@ static void pnv_chip_power10_realize(DeviceState *dev,
Error **errp)
&PNV_PSI(&chip10->psi)->xscom_regs);
/* LPC */
- object_property_set_link(OBJECT(&chip10->lpc), "psi",
- OBJECT(&chip10->psi), &error_abort);
if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
return;
}
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index bcbca3db9743..ee890e7ab419 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -422,7 +422,6 @@ static const MemoryRegionOps pnv_lpc_mmio_ops = {
static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
{
bool lpc_to_opb_irq = false;
- PnvLpcClass *plc = PNV_LPC_GET_CLASS(lpc);
/* Update LPC controller to OPB line */
if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
@@ -445,7 +444,7 @@ static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
/* Reflect the interrupt */
- pnv_psi_irq_set(lpc->psi, plc->psi_irq, lpc->opb_irq_stat != 0);
+ qemu_set_irq(lpc->psi_irq, lpc->opb_irq_stat != 0);
}
static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
@@ -637,8 +636,6 @@ static void pnv_lpc_power8_class_init(ObjectClass *klass,
void *data)
xdc->dt_xscom = pnv_lpc_dt_xscom;
- plc->psi_irq = PSIHB_IRQ_LPC_I2C;
-
device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
&plc->parent_realize);
}
@@ -677,8 +674,6 @@ static void pnv_lpc_power9_class_init(ObjectClass *klass,
void *data)
dc->desc = "PowerNV LPC Controller POWER9";
- plc->psi_irq = PSIHB9_IRQ_LPCHC;
-
device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
&plc->parent_realize);
}
@@ -706,8 +701,6 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
{
PnvLpcController *lpc = PNV_LPC(dev);
- assert(lpc->psi);
-
/* Reg inits */
lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
@@ -746,12 +739,9 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
"lpc-hc", LPC_HC_REGS_OPB_SIZE);
memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
&lpc->lpc_hc_regs);
-}
-static Property pnv_lpc_properties[] = {
- DEFINE_PROP_LINK("psi", PnvLpcController, psi, TYPE_PNV_PSI, PnvPsi *),
- DEFINE_PROP_END_OF_LIST(),
-};
+ qdev_init_gpio_out(DEVICE(dev), &lpc->psi_irq, 1);
+}
static void pnv_lpc_class_init(ObjectClass *klass, void *data)
{
@@ -759,7 +749,6 @@ static void pnv_lpc_class_init(ObjectClass *klass, void
*data)
dc->realize = pnv_lpc_realize;
dc->desc = "PowerNV LPC Controller";
- device_class_set_props(dc, pnv_lpc_properties);
dc->user_creatable = false;
}
@@ -803,7 +792,7 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int
n, int level)
}
if (pnv->cpld_irqstate != old_state) {
- pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
+ qemu_set_irq(lpc->psi_irq, pnv->cpld_irqstate != 0);
}
}
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index c588a506c7cc..8b6298d4bd96 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -216,6 +216,12 @@ void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
}
+static void __pnv_psi_irq_set(void *opaque, int irq, int state)
+{
+ PnvPsi *psi = (PnvPsi *) opaque;
+ PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
+}
+
static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
{
uint32_t xivr_reg;
@@ -512,6 +518,8 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error
**errp)
ics_set_irq_type(ics, i, true);
}
+ qdev_init_gpio_in(dev, __pnv_psi_irq_set, ics->nr_irqs);
+
psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
/* XSCOM region for PSI registers */
@@ -873,6 +881,8 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error
**errp)
psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
+ qdev_init_gpio_in(dev, __pnv_psi_irq_set, xsrc->nr_irqs);
+
/* XSCOM region for PSI registers */
pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
--
2.34.1
- [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device, Cédric Le Goater, 2022/03/23
- [PATCH 5/5] ppc/pnv: Remove usless checks in set_irq handlers, Cédric Le Goater, 2022/03/23
- [PATCH 1/5] ppc/pnv: Fix PSI IRQ definition, Cédric Le Goater, 2022/03/23
- [PATCH 3/5] ppc/pnv: Remove PnvOCC::psi link, Cédric Le Goater, 2022/03/23
- [PATCH 4/5] ppc/pnv: Remove PnvPsiClas::irq_set, Cédric Le Goater, 2022/03/23
- [PATCH 2/5] ppc/pnv: Remove PnvLpcController::psi link,
Cédric Le Goater <=
- Re: [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device, Daniel Henrique Barboza, 2022/03/24