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Re: [RFC PATCH 1/6] target/ppc: Add support for the Processor Attention
From: |
David Gibson |
Subject: |
Re: [RFC PATCH 1/6] target/ppc: Add support for the Processor Attention instruction |
Date: |
Sat, 26 Mar 2022 14:15:14 +1100 |
On Fri, Mar 25, 2022 at 12:11:47PM -0300, Fabiano Rosas wrote:
> Leandro Lupori <leandro.lupori@eldorado.org.br> writes:
>
> > From: Cédric Le Goater <clg@kaod.org>
> >
> > Check the HID0 bit to send signal, currently modeled as a checkstop.
> > The QEMU implementation adds an exit using the GPR[3] value (that's a
> > hack for tests)
> >
> > Signed-off-by: Cédric Le Goater <clg@kaod.org>
> > Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
> > ---
> > target/ppc/cpu.h | 8 ++++++++
> > target/ppc/excp_helper.c | 27 +++++++++++++++++++++++++++
> > target/ppc/helper.h | 1 +
> > target/ppc/translate.c | 14 ++++++++++++++
> > 4 files changed, 50 insertions(+)
> >
> > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > index 047b24ba50..12f9f3a880 100644
> > --- a/target/ppc/cpu.h
> > +++ b/target/ppc/cpu.h
> > @@ -173,6 +173,12 @@ enum {
> > POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception
> > */
> > /* Trap
> > */
> > POWERPC_EXCP_TRAP = 0x40,
> > + /* Processor Attention
> > */
> > + POWERPC_EXCP_ATTN = 0x100,
> > + /*
> > + * NOTE: POWERPC_EXCP_ATTN uses values from 0x100 to 0x1ff to return
> > + * error codes.
> > + */
> > };
> >
> > #define PPC_INPUT(env) ((env)->bus_model)
> > @@ -2089,6 +2095,8 @@ void ppc_compat_add_property(Object *obj, const char
> > *name,
> > #define HID0_DOZE (1 << 23) /* pre-2.06 */
> > #define HID0_NAP (1 << 22) /* pre-2.06 */
> > #define HID0_HILE PPC_BIT(19) /* POWER8 */
> > +#define HID0_ATTN PPC_BIT(31) /* Processor Attention */
> > +#define HID0_POWER9_ATTN PPC_BIT(3)
> > #define HID0_POWER9_HILE PPC_BIT(4)
> >
> >
> > /*****************************************************************************/
> > diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> > index d3e2cfcd71..b0c629905c 100644
> > --- a/target/ppc/excp_helper.c
> > +++ b/target/ppc/excp_helper.c
> > @@ -1379,6 +1379,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int
> > excp)
> > }
> > cs->halted = 1;
> > cpu_interrupt_exittb(cs);
> > + if ((env->error_code & ~0xff) == POWERPC_EXCP_ATTN) {
> > + exit(env->error_code & 0xff);
> > + }
> > }
> > if (env->msr_mask & MSR_HVB) {
> > /*
> > @@ -1971,6 +1974,30 @@ void helper_pminsn(CPUPPCState *env,
> > powerpc_pm_insn_t insn)
> > env->resume_as_sreset = (insn != PPC_PM_STOP) ||
> > (env->spr[SPR_PSSCR] & PSSCR_EC);
> > }
> > +
> > +/*
> > + * Processor Attention instruction (Implementation dependent)
> > + */
> > +void helper_attn(CPUPPCState *env, target_ulong r3)
> > +{
> > + bool attn = false;
> > +
> > + if (env->excp_model == POWERPC_EXCP_POWER8) {
> > + attn = !!(env->spr[SPR_HID0] & HID0_ATTN);
> > + } else if (env->excp_model == POWERPC_EXCP_POWER9 ||
> > + env->excp_model == POWERPC_EXCP_POWER10) {
> > + attn = !!(env->spr[SPR_HID0] & HID0_POWER9_ATTN);
> > + }
>
> The excp_model is not a CPU identifier. This should ideally be a flag
> set during init_proc. Something like HID0_ATTN_P8/HID0_ATTN_P9.
>
> Maybe we should consider adding a hid0_mask similar to lpcr_mask.
I don't think that's a good idea. By definition, the meaning of the
HID registers is model specific - having a hid0_mask would imply it
always has the same meaning, just different bits that are present or
not. I think you want to explicitly dispath to cpu family specific
functions for this.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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[RFC PATCH 5/6] tests/tcg/ppc64: add MMU test sources, Leandro Lupori, 2022/03/24