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Re: [RFC PATCH 0/6] Port PPC64/PowerNV MMU tests to QEMU
From: |
Fabiano Rosas |
Subject: |
Re: [RFC PATCH 0/6] Port PPC64/PowerNV MMU tests to QEMU |
Date: |
Mon, 28 Mar 2022 11:54:39 -0300 |
Richard Henderson <richard.henderson@linaro.org> writes:
> On 3/24/22 13:08, Leandro Lupori wrote:
>> To be able to finish the test and return an exit code to the
>> calling process, the Processor Attention instruction is used.
>> As its behavior is implementation dependent, in QEMU PowerNV
>> it just calls exit with GPR[3] value, truncated to an uint8_t.
>
> I think you're simply thinking too small here, and should consider using the
> attn
> instruction to implement a full -semihosting interface. You might as well
> join arm and
> riscv with CONFIG_ARM_COMPATIBLE_SEMIHOSTING.
I can't reach the semihosting docs at:
https://static.docs.arm.com/100863/0200/semihosting.pdf
Do we need to replace that URL with something else?
>
>
> r~
- [RFC PATCH 2/6] ppc/pnv: Activate support for the Processor Attention instruction, (continued)
[RFC PATCH 5/6] tests/tcg/ppc64: add MMU test sources, Leandro Lupori, 2022/03/24
[RFC PATCH 6/6] tests/tcg/ppc64: add rules to build PowerNV tests, Leandro Lupori, 2022/03/24
Re: [RFC PATCH 0/6] Port PPC64/PowerNV MMU tests to QEMU, Richard Henderson, 2022/03/26