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[RFC PATCH 6/6] target/ppc: implement xscvqp[su]qz
From: |
matheus . ferst |
Subject: |
[RFC PATCH 6/6] target/ppc: implement xscvqp[su]qz |
Date: |
Mon, 28 Mar 2022 17:14:42 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
xscvqpsqz: VSX Scalar Convert with round to zero Quad-Precision to
Signed Quadword
xscvqpuqz: VSX Scalar Convert with round to zero Quad-Precision to
Unsigned Quadword
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/fpu_helper.c | 23 +++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode | 2 ++
target/ppc/translate/vsx-impl.c.inc | 2 ++
4 files changed, 29 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 5101ba92ae..712306b5a1 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2925,6 +2925,29 @@ VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32,
VsrW(i), VsrW(i), 0x80000000U)
VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
+#define VSX_CVT_FP_TO_INT128(op, tp, rnan) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
+{ \
+ ppc_vsr_t t; \
+ int flags; \
+ \
+ helper_reset_fpstatus(env); \
+ t.VsrD(0) = float128_to_##tp##_round_to_zero(xb->f128, &env->fp_status, \
+ &t.VsrD(1)); \
+ flags = get_float_exception_flags(&env->fp_status); \
+ if (unlikely(flags & float_flag_invalid)) { \
+ t.VsrD(0) = float_invalid_cvt(env, flags, t.VsrD(0), rnan, 0, \
+ GETPC()); \
+ t.VsrD(1) = -(t.VsrD(0) & 1); \
+ } \
+ \
+ *xt = t; \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_FP_TO_INT128(XSCVQPUQZ, uint128, 0)
+VSX_CVT_FP_TO_INT128(XSCVQPSQZ, int128, 0x8000000000000000ULL);
+
/*
* Likewise, except that the result is duplicated into both subwords.
* Power ISA v3.1 has Programming Notes for these insns:
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 7df0c01819..aa6773c4a5 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -388,6 +388,8 @@ DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscvqpuwz, void, env, i32, vsr, vsr)
+DEF_HELPER_3(XSCVQPUQZ, void, env, vsr, vsr)
+DEF_HELPER_3(XSCVQPSQZ, void, env, vsr, vsr)
DEF_HELPER_3(XSCVUQQP, void, env, vsr, vsr)
DEF_HELPER_3(XSCVSQQP, void, env, vsr, vsr)
DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 6fb568c1fe..39372fe673 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -695,6 +695,8 @@ XSCMPGTQP 111111 ..... ..... ..... 0011100100 - @X
## VSX Binary Floating-Point Convert Instructions
XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
+XSCVQPUQZ 111111 ..... 00000 ..... 1101000100 - @X_tb
+XSCVQPSQZ 111111 ..... 01000 ..... 1101000100 - @X_tb
XSCVUQQP 111111 ..... 00011 ..... 1101000100 - @X_tb
XSCVSQQP 111111 ..... 01011 ..... 1101000100 - @X_tb
XVCVBF16SPN 111100 ..... 10000 ..... 111011011 .. @XX2
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index a305579ecc..5cc006d715 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -855,6 +855,8 @@ static bool do_helper_env_X_tb(DisasContext *ctx, arg_X_tb
*a,
return true;
}
+TRANS(XSCVQPUQZ, do_helper_env_X_tb, gen_helper_XSCVQPUQZ)
+TRANS(XSCVQPSQZ, do_helper_env_X_tb, gen_helper_XSCVQPSQZ)
TRANS(XSCVUQQP, do_helper_env_X_tb, gen_helper_XSCVUQQP)
TRANS(XSCVSQQP, do_helper_env_X_tb, gen_helper_XSCVSQQP)
--
2.25.1
- [RFC PATCH 1/6] softfloat: add uint128_to_float* conversion methods, (continued)
- [RFC PATCH 1/6] softfloat: add uint128_to_float* conversion methods, matheus . ferst, 2022/03/28
- [RFC PATCH 2/6] softfloat: add int128_to_float* conversion methods, matheus . ferst, 2022/03/28
- [RFC PATCH 3/6] softfloat: add float*_to_uint128 conversion methods, matheus . ferst, 2022/03/28
- [RFC PATCH 4/6] softfloat: add float*_to_int128 conversion methods, matheus . ferst, 2022/03/28
- [RFC PATCH 5/6] target/ppc: implement xscv[su]qqp, matheus . ferst, 2022/03/28
- [RFC PATCH 6/6] target/ppc: implement xscvqp[su]qz,
matheus . ferst <=
- Re: [RFC PATCH 0/6] softfloat 128-bit integer support, Richard Henderson, 2022/03/28