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[PATCH 09/10] target/ppc: Implemented vector module word/doubleword
From: |
Lucas Mateus Castro(alqotel) |
Subject: |
[PATCH 09/10] target/ppc: Implemented vector module word/doubleword |
Date: |
Wed, 30 Mar 2022 17:25:14 -0300 |
From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
vmodsw: Vector Modulo Signed Word
vmoduw: Vector Modulo Unsigned Word
vmodsd: Vector Modulo Signed Doubleword
vmodud: Vector Modulo Unsigned Doubleword
Hardware behavior based on mambo.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
---
target/ppc/insn32.decode | 5 +++++
target/ppc/translate/vmx-impl.c.inc | 26 ++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 3eb920ac76..36b42e41d2 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -719,3 +719,8 @@ VDIVESD 000100 ..... ..... ..... 01111001011 @VX
VDIVEUD 000100 ..... ..... ..... 01011001011 @VX
VDIVESQ 000100 ..... ..... ..... 01100001011 @VX
VDIVEUQ 000100 ..... ..... ..... 01000001011 @VX
+
+VMODSW 000100 ..... ..... ..... 11110001011 @VX
+VMODUW 000100 ..... ..... ..... 11010001011 @VX
+VMODSD 000100 ..... ..... ..... 11111001011 @VX
+VMODUD 000100 ..... ..... ..... 11011001011 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 62b2fcd45c..ed01d91b87 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -3349,6 +3349,27 @@ static void do_vx_diveu_i32(TCGv_i32 t, TCGv_i32 a,
TCGv_i32 b)
tcg_temp_free_i64(val2);
}
+#define REM_VEC(NAME, SZ, REM) \
+static void do_vx_##NAME(TCGv_##SZ t, TCGv_##SZ a, TCGv_##SZ b) \
+{ \
+ TCGv_##SZ zero = tcg_constant_##SZ(0), one = tcg_constant_##SZ(1); \
+ /* \
+ * If N%0 the instruction used by the backend might deliver \
+ * a signal to the process and the hardware returns 0 when \
+ * N%0, so if b = 0 return 0%1 \
+ */ \
+ tcg_gen_movcond_##SZ(TCG_COND_EQ, a, b, zero, zero, a); \
+ tcg_gen_movcond_##SZ(TCG_COND_EQ, b, b, zero, one, b); \
+ REM(t, a, b); \
+}
+
+REM_VEC(rem_i32 , i32, tcg_gen_rem_i32)
+REM_VEC(remu_i32, i32, tcg_gen_remu_i32)
+REM_VEC(rem_i64 , i64, tcg_gen_rem_i64)
+REM_VEC(remu_i64, i64, tcg_gen_remu_i64)
+
+#undef REM_VEC
+
TRANS_VDIV_VMOD(ISA310, VDIVESW, MO_32, do_vx_dives_i32, NULL)
TRANS_VDIV_VMOD(ISA310, VDIVEUW, MO_32, do_vx_diveu_i32, NULL)
TRANS_FLAGS2(ISA310, VDIVESD, do_vx_helper, gen_helper_VDIVESD)
@@ -3356,6 +3377,11 @@ TRANS_FLAGS2(ISA310, VDIVEUD, do_vx_helper,
gen_helper_VDIVEUD)
TRANS_FLAGS2(ISA310, VDIVESQ, do_vx_helper, gen_helper_VDIVESQ)
TRANS_FLAGS2(ISA310, VDIVEUQ, do_vx_helper, gen_helper_VDIVEUQ)
+TRANS_VDIV_VMOD(ISA310, VMODSW, MO_32, do_vx_rem_i32 , NULL)
+TRANS_VDIV_VMOD(ISA310, VMODUW, MO_32, do_vx_remu_i32, NULL)
+TRANS_VDIV_VMOD(ISA310, VMODSD, MO_64, NULL, do_vx_rem_i64)
+TRANS_VDIV_VMOD(ISA310, VMODUD, MO_64, NULL, do_vx_remu_i64)
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
--
2.31.1
- [PATCH 03/10] target/ppc: Implemented vector divide instructions, (continued)
- [PATCH 03/10] target/ppc: Implemented vector divide instructions, Lucas Mateus Castro(alqotel), 2022/03/30
- [PATCH 04/10] target/ppc: Implemented vector divide quadword, Lucas Mateus Castro(alqotel), 2022/03/30
- [PATCH 05/10] target/ppc: Implemented vector divide extended word, Lucas Mateus Castro(alqotel), 2022/03/30
- [PATCH 06/10] Implemented unsigned 256-by-128 division, Lucas Mateus Castro(alqotel), 2022/03/30
- [PATCH 07/10] Implemented signed 256-by-128 division, Lucas Mateus Castro(alqotel), 2022/03/30
- [PATCH 08/10] target/ppc: Implemented remaining vector divide extended, Lucas Mateus Castro(alqotel), 2022/03/30
- [PATCH 09/10] target/ppc: Implemented vector module word/doubleword,
Lucas Mateus Castro(alqotel) <=
- [PATCH 10/10] target/ppc: Implemented vector module quadword, Lucas Mateus Castro(alqotel), 2022/03/30