[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 04/62] target/ppc: move msgclr/msgsnd to decodetree
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 04/62] target/ppc: move msgclr/msgsnd to decodetree |
Date: |
Fri, 28 Oct 2022 13:38:53 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20221006200654.725390-5-matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/insn32.decode | 5 ++
target/ppc/translate.c | 34 +--------
.../ppc/translate/processor-ctrl-impl.c.inc | 70 +++++++++++++++++++
3 files changed, 77 insertions(+), 32 deletions(-)
create mode 100644 target/ppc/translate/processor-ctrl-impl.c.inc
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a5249ee32c..bba49ded1b 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -908,3 +908,8 @@ SLBSYNC 011111 ----- ----- ----- 0101010010 -
TLBIE 011111 ..... - .. . . ..... 0100110010 - @X_tlbie
TLBIEL 011111 ..... - .. . . ..... 0100010010 - @X_tlbie
+
+# Processor Control Instructions
+
+MSGCLR 011111 ----- ----- ..... 0011101110 - @X_rb
+MSGSND 011111 ----- ----- ..... 0011001110 - @X_rb
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f73ff2d2ee..231bc9551e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6241,34 +6241,6 @@ static void gen_icbt_440(DisasContext *ctx)
/* Embedded.Processor Control */
-static void gen_msgclr(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_HV(ctx);
- if (is_book3s_arch2x(ctx)) {
- gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
- } else {
- gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
- }
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-static void gen_msgsnd(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV(ctx);
-#else
- CHK_HV(ctx);
- if (is_book3s_arch2x(ctx)) {
- gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
- } else {
- gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
- }
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
#if defined(TARGET_PPC64)
static void gen_msgclrp(DisasContext *ctx)
{
@@ -6628,6 +6600,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d,
arg_PLS_D *a)
#include "translate/branch-impl.c.inc"
+#include "translate/processor-ctrl-impl.c.inc"
+
#include "translate/storage-ctrl-impl.c.inc"
/* Handles lfdp */
@@ -6901,10 +6875,6 @@ GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12,
0x18, 0x00000001,
PPC_NONE, PPC2_BOOKE206),
GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
PPC_NONE, PPC2_BOOKE206),
-GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
- PPC_NONE, (PPC2_PRCNTL | PPC2_ISA207S)),
-GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
- PPC_NONE, (PPC2_PRCNTL | PPC2_ISA207S)),
GEN_HANDLER2_E(msgsync, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
PPC_NONE, PPC2_ISA300),
GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc
b/target/ppc/translate/processor-ctrl-impl.c.inc
new file mode 100644
index 0000000000..208f2c2391
--- /dev/null
+++ b/target/ppc/translate/processor-ctrl-impl.c.inc
@@ -0,0 +1,70 @@
+/*
+ * Power ISA decode for Storage Control instructions
+ *
+ * Copyright (c) 2022 Instituto de Pesquisas Eldorado (eldorado.org.br)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Processor Control Instructions
+ */
+
+static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a)
+{
+ if (!(ctx->insns_flags2 & PPC2_ISA207S)) {
+ /*
+ * Before Power ISA 2.07, processor control instructions were only
+ * implemented in the "Embedded.Processor Control" category.
+ */
+ REQUIRE_INSNS_FLAGS2(ctx, PRCNTL);
+ }
+
+ REQUIRE_HV(ctx);
+
+#if !defined(CONFIG_USER_ONLY)
+ if (is_book3s_arch2x(ctx)) {
+ gen_helper_book3s_msgclr(cpu_env, cpu_gpr[a->rb]);
+ } else {
+ gen_helper_msgclr(cpu_env, cpu_gpr[a->rb]);
+ }
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a)
+{
+ if (!(ctx->insns_flags2 & PPC2_ISA207S)) {
+ /*
+ * Before Power ISA 2.07, processor control instructions were only
+ * implemented in the "Embedded.Processor Control" category.
+ */
+ REQUIRE_INSNS_FLAGS2(ctx, PRCNTL);
+ }
+
+ REQUIRE_HV(ctx);
+
+#if !defined(CONFIG_USER_ONLY)
+ if (is_book3s_arch2x(ctx)) {
+ gen_helper_book3s_msgsnd(cpu_gpr[a->rb]);
+ } else {
+ gen_helper_msgsnd(cpu_gpr[a->rb]);
+ }
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.37.3
- [PULL 00/62] ppc queue, Daniel Henrique Barboza, 2022/10/28
- [PULL 01/62] target/ppc: fix msgclr/msgsnd insns flags, Daniel Henrique Barboza, 2022/10/28
- [PULL 03/62] target/ppc: fix REQUIRE_HV macro definition, Daniel Henrique Barboza, 2022/10/28
- [PULL 04/62] target/ppc: move msgclr/msgsnd to decodetree,
Daniel Henrique Barboza <=
- [PULL 06/62] target/ppc: move msgsync to decodetree, Daniel Henrique Barboza, 2022/10/28
- [PULL 02/62] target/ppc: fix msgsync insns flags, Daniel Henrique Barboza, 2022/10/28
- [PULL 05/62] target/ppc: move msgclrp/msgsndp to decodetree, Daniel Henrique Barboza, 2022/10/28
- [PULL 07/62] target/ppc: Moved VMLADDUHM to decodetree and use gvec, Daniel Henrique Barboza, 2022/10/28
- [PULL 08/62] target/ppc: Move VMH[R]ADDSHS instruction to decodetree, Daniel Henrique Barboza, 2022/10/28
- [PULL 09/62] target/ppc: Move V(ADD|SUB)CUW to decodetree and use gvec, Daniel Henrique Barboza, 2022/10/28
- [PULL 15/62] target/ppc: Use gvec to decode XVCPSGN[SD]P, Daniel Henrique Barboza, 2022/10/28
- [PULL 18/62] target/ppc: Use gvec to decode XVTSTDC[DS]P, Daniel Henrique Barboza, 2022/10/28
- [PULL 14/62] target/ppc: Use gvec to decode XV[N]ABS[DS]P/XVNEG[DS]P, Daniel Henrique Barboza, 2022/10/28
- [PULL 11/62] target/ppc: Move VPRTYB[WDQ] to decodetree and use gvec, Daniel Henrique Barboza, 2022/10/28