Re: [PULL 00/15] ppc queue

[Philippe Mathieu-Daudé]

On 20/12/22 22:34, Peter Maydell wrote:
> On Tue, 20 Dec 2022 at 13:53, Daniel Henrique Barboza
> <danielhb413@gmail.com> wrote:

> This fails 'make check'; I think the sdhci changes have
> broken the npmcm7xx-sdhci device:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/3504313175
>
> 46/106 ERROR:../tests/qtest/npcm7xx_sdhci-test.c:101:sdwrite_read:
> assertion failed: (!memcmp(rmsg, msg, len)) ERROR
> 46/106 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_sdhci-test ERROR 1.67s
> killed by signal 6 SIGABRT

5218b3960738a6da041aa6f54ac4b37566311cca is the first bad commit
commit 5218b3960738a6da041aa6f54ac4b37566311cca
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date:   Tue Nov 1 23:29:32 2022 +0100

    hw/sd/sdhci: MMIO region is implemented in 32-bit accesses
@@ -14,2898 +14,914 @@
 sdcard_reset
 sdcard_reset
 sdhci_set_inserted card state changed: insert
-memory_region_ops_write cpu -1 mr 0x1581ff440 addr 0xf084202f value 0x1 
size 1 name 'sdhci'
+memory_region_ops_write cpu -1 mr 0x1481ff440 addr 0xf084202f value 0x1 
size 4 name 'sdhci'
 sdhci_set_inserted card state changed: insert
-sdhci_access wr8: addr[0x002f] <- 0x00000001 (1)
-memory_region_ops_write cpu -1 mr 0x1581ff440 addr 0xf0842030 value 0x0 
size 1 name 'sdhci'
-sdhci_access wr8: addr[0x0030] <- 0x00000000 (0)
-memory_region_ops_write cpu -1 mr 0x1581ff440 addr 0xf084202c value 0x7 
size 2 name 'sdhci'
-sdhci_access wr16: addr[0x002c] <- 0x00000007 (7)
-memory_region_ops_write cpu -1 mr 0x1581ff440 addr 0xf0842004 value 0x0 
size 2 name 'sdhci'
-sdhci_access wr16: addr[0x0004] <- 0x00000000 (0)
-memory_region_ops_write cpu -1 mr 0x1581ff440 addr 0xf0842006 value 0x0 
size 2 name 'sdhci'
-sdhci_access wr16: addr[0x0006] <- 0x00000000 (0)
-memory_region_ops_write cpu -1 mr 0x1581ff440 addr 0xf0842008 value 0x0 
size 4 name 'sdhci'
+sdhci_access wr32: addr[0x002f] <- 0x00000001 (1)
+memory_region_ops_write cpu -1 mr 0x1481ff440 addr 0xf0842030 value 0x0 
size 4 name 'sdhci'
+sdhci_access wr32: addr[0x0030] <- 0x00000000 (0)
+memory_region_ops_write cpu -1 mr 0x1481ff440 addr 0xf084202c value 0x7 
size 4 name 'sdhci'
+sdhci_access wr32: addr[0x002c] <- 0x00000007 (7)
+memory_region_ops_write cpu -1 mr 0x1481ff440 addr 0xf0842004 value 0x0 
size 4 name 'sdhci'
+sdhci_access wr32: addr[0x0004] <- 0x00000000 (0)
+memory_region_ops_write cpu -1 mr 0x1481ff440 addr 0xf0842006 value 0x0 
size 4 name 'sdhci'
+sdhci_access wr32: addr[0x0006] <- 0x00000000 (0)
+memory_region_ops_write cpu -1 mr 0x1481ff440 addr 0xf0842008 value 0x0 
size 4 name 'sdhci'
 sdhci_access wr32: addr[0x0008] <- 0x00000000 (0)
-memory_region_ops_write cpu -1 mr 0x1581ff440 addr 0xf084200c value 0x0 
size 2 name 'sdhci'
-sdhci_access wr16: addr[0x000c] <- 0x00000000 (0)
-memory_region_ops_write cpu -1 mr 0x1581ff440 addr 0xf084200e value 
0x3700 size 2 name 'sdhci'
+memory_region_ops_write cpu -1 mr 0x1481ff440 addr 0xf084200c value 0x0 
size 4 name 'sdhci'

Apparently we aren't modeling some bus translator on the NPCM7xx.

Daniel, I apologize. Could you respin without the "hw/sd/sdhci:
MMIO region is implemented in 32-bit accesses" patch?

Thanks,

Phil.